• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.301-308
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• 2011

This paper deals with the coupled electromagnetic-mechanical field analysis for short-circuit electromagnetic force of the dry-type transformer. The short-circuit currents are calculated using external circuit in accordance with short-circuit test equipment. According to short-circuit current, the generated magnetic leakage flux density in dry-type transformer model is calculated by finite element method. The radially-directed electromagnetic forces in windings are calculated using electromagnetic field analysis and then axially-directed electromagnetic forces in windings are calculated using electromagnetic-mechanical field analysis. The calculated axially-directed electromagnetic forces in high voltage winding are compared to those of measured ones and showed good agreement with experimental results.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.5
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• pp.281-284
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• 1999

In this paper, the electrical conduction, breakdown strength and dielectric properties were investigated in the interfaces of PET films. The volume resistivity and breakdown strength were decreased; especially the specimens with semiconductive layer showed the lowest breakdown strength. This decrease of electrical properties was appeared by increasing charge density in inhomogeneous layer of PET. The dielectric properties of PET did not show significant difference with PET/PET but the films with semiconductive interface layer showed the increase in capacitance and $tan\delta$ was affected by the PET rather than semiconductive layer. It is assumed that the variation of $tan\delta$ was affected by the dielectric polarization and the leakage current(charge).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.05c
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• pp.83-87
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• 2002

Plasma enhanced chemical vapor deposited (PECVD) silicon nitride ($SiN_X$) is widely used as a gate dielectric material for the hydrogenated amorphous silicon(a-Si:H) thin film transistors (TFT's). We investigated $SiN_X$ films were deposited PECVD at low temperature ($300^{\circ}C$). The reaction gases were used pure nitrogen and a helium diluted of silane gas(20% $SiH_4$, 80% He). Experimental investigations were carried out with the variation of $N_2/SiH_4$ flow ratios from 3 to 50 and the rf power of 200 W. This article presents the $SiN_X$ gate dielectric studies in terms of deposition rate, hydrogen content, etch rate and C-V, leakage current density characteristics for the gate dielectric layer of thin film transistor applications. Electrical properties were analyzed through high frequency (1MHz) C-V and current-voltage (I-V) measurements. The thickness and the refractive index on the films were measured by ellipsometry and chemical bonds were determined by using an FT-IR equipment.

• Journal of Radiation Protection and Research
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• v.28 no.2
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• pp.87-95
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• 2003

The fabrication process and the structure of PIN semiconductor detectors have been designed optimally by simulation for doping concentration and width of p+ layer, impurities re-contribution due to annealing and the current distribution due to guard ring at the sliced edges. The characteristics to radiation response has been also simulated in terms of Monte Carlo Method. The device has been fabricated on n type, $400\;{\Omega}cm$, orientation <100>, Floating-Zone silicon wafer using the simulation results. The leakage current density of $0.7nA/cm^2/100{\mu}m$ is achieved by this process. The good linearity of radiation response to Cs-137 was kept within the exposure ranges between 5 mR/h and 25 R/h. This proposed process could be applied for fabricating a PIN semiconductor detector for measuring individual dose.

• Korean Journal of Materials Research
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• v.29 no.8
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• pp.463-468
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• 2019

The electrical and interfacial properties of $HfO_2/Al_2O_3$ and $Al_2O_3/HfO_2$ dielectrics on AlN/p-Ge interface prepared by thermal atomic layer deposition are investigated by capacitance-voltage(C-V) and current-voltage(I-V) measurements. In the C-V measurements, humps related to mid-gap states are observed when the ac frequency is below 100 kHz, revealing lower mid-gap states for the $HfO_2/Al_2O_3$ sample. Higher frequency dispersion in the inversion region is observed for the $Al_2O_3/HfO_2$ sample, indicating the presence of slow interface states A higher interface trap density calculated from the high-low frequency method is observed for the $Al_2O_3/HfO_2$ sample. The parallel conductance method, applied to the accumulation region, shows border traps at 0.3~0.32 eV for the $Al_2O_3/HfO_2$ sample, which are not observed for the $Al_2O_3/HfO_2$ sample. I-V measurements show a reduction of leakage current of about three orders of magnitude for the $HfO_2/Al_2O_3$ sample. Using the Fowler-Nordheim emission, the barrier height is calculated and found to be about 1.08 eV for the $HfO_2/Al_2O_3$ sample. Based on these results, it is suggested that $HfO_2/Al_2O_3$ is a better dielectric stack than $Al_2O_3/HfO_2$ on AlN/p-Ge interface.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.9
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• pp.825-831
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• 2006

As an increase of chip complexity and level of chip integration, chip input/output (I/O) pad pitches are also drastically reduced. With arrival of high complexity SoC (System on Chip) and SiP (System in Package) products, conventional horizontal type probe card showed its limitation on probing density for wafer level test. To enhance probing density, we proposed new vertical type probe card that has the $70{\mu}m$ probe needle with tungsten wire in $80{\mu}m$ micro-drilled hole in ceramic board. To minimize alignment error, micro-drilling conditions are optimized and epoxy-hardening conditions are also optimized to minimize planarity changes. To apply wafer level test for target devices (T5365 256M SDRAM), designed probe card was characterized by probe needle tension for test, contact resistance measurement, leakage current measurement and the planarity test. Compare to conventional probe card with minimum pitch of $50{\sim}125{\mu}m\;and\;2\;{\Omega}$ of average contact resistance, designed probe card showed only $22{\mu}$ of minimum pitch and $1.5{\Omega}$ of average contact resistance. And also, with the nature of vertical probing style, it showed comparably small contact scratch and it can be applied to bumping type chip test.

• Korean Journal of Materials Research
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• v.17 no.2
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• pp.81-85
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• 2007

Embedded capacitor technology can improve electrical perfomance and reduce assembly cost compared with traditional discrete capacitor technology. To improve the capacitance density of the $Al_2O_3$ based embedded capacitor on Cu cladded fiber reinforced plastics (FR-4), the specific surface area of the $Al_2O_3$ thin films was enlarged and their surface morphologies were controlled by anodization process parameters. From I-V characteristics, it was found that breakdown voltage and leakage current were 23 V and $1{\times}10^{-6}A/cm^2$ at 3.3 V, respectively. We have also measured C-V characteristics of $Pt/Al_2O_3/Al/Ti$ structure on CU/FR4. The capacitance density was $300nF/cm^2$ and the dielectric loss was 0.04. This nano-porous $Al_2O_3$ is a good material candidate for the embedded capacitor application for electronic products.

• Korean Journal of Materials Research
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• v.25 no.1
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• pp.37-42
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• 2015

The effect of sintering temperature on the microstructure, electrical and dielectric properties of (V, Mn, Co, Dy, Bi)-codoped zinc oxide ceramics was investigated in this study. An increase in the sintering temperature increased the average grain size from 4.7 to $10.4{\mu}m$ and decreased the sintered density from 5.47 to $5.37g/cm^3$. As the sintering temperature increased, the breakdown field decreased greatly from 6027 to 1659 V/cm. The ceramics sintered at $900^{\circ}C$ were characterized by the highest nonlinear coefficient (36.2) and the lowest low leakage current density ($36.4{\mu}A/cm^2$). When the sintering temperature increased, the donor concentration of the semiconducting grain increased from $2.49{\times}10^{17}$ to $6.16{\times}10^{17}/cm^3$, and the density of interface state increased from $1.34{\times}10^{12}$ to $1.99{\times}10^{12}/cm^2$. The dielectric constant increased greatly from 412.3 to 1234.8 with increasing sintering temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• International Journal of Internet, Broadcasting and Communication
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• v.10 no.4
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• pp.6-11
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• 2018

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation.These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.