• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.80-81
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• 2008

Schottky barrier thin film transistors (SB-TFT) on polycrystalline silicon(poly-Si) are fabricated by platinum silicided source/drain for p-type SB-TFT. High quality poly-Si film were obtained by crystallizing the amorphous Si film with excimer laser annealing (ELA) or solid phase crystallization (SPC) method. The fabricated poly-Si SB-TFTs showed low leakage current level and a large on/off current ratio larger than $10^5$. Significant improvement of electrical characteristics were obtained by the additional forming gas annealing in 2% $H_2/N_2$ ambient, which is attributed to the termination of dangling bond at the poly-Si grain boundaries as well as the reduction of interface trap states at gate oxide/poly-Si channel.

• Biomolecules & Therapeutics
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• v.8 no.1
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• pp.63-72
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• 2000

We intended to show some basic requirements for spectrum analysis of electroencephalogram (EEG) by visualizing the differences of the results according to different values of some parameters for analysis. Spectrum analysis is the most popular technique applied for the quantitative analysis of the electroen- cephalographic signals. Each step from signal acquisition through spectrum analysis to presentation of parameters was examined with providing some different values of parameters. The steps are:(1) signal acquisition; (2) spectrum analysis; (3) parameter extractions; and (4) presentation of results. In the step of signal acquisition, filtering and amplification of signal should be considered and sampling rate for analog-to-digital conversion is two-time faster than highest frequency component of signal. For the spectrum analysis, the length of signal or epoch size transformed to a function on frequency domain by courier transform is important. Win dowing method applied for the pre-processing before the analysis should be considered for reducing leakage problem. In the step of parameter extraction, data reduction has to be considered so that statistical comparison can be used in appropriate number of parameters. Generally, the log of power of all bands is derived from the spectrum. For good visualization and quantitative evaluation of time course of the parameters are presented in chronospectrogram.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.24 no.3 s.174
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• pp.728-734
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• 2000

An asymmetric actuator can be used to reduce the distance between the reflective mirror and objective lens of a small optical disk drive for use in the notebook-sized personal computer data storage devices. However, this asymmetric actuator is very sensitive to the subsidiary resonance which is caused by its rigid body motion. In this paper, an analytical approach using a simple lumped parameter system model is presented with a physical insight to investigate why the subsidiary resonance occurs. The finite element method is used to figure out the force and torque characteristics of the asymmetric actuator which are essential to understand the subsidiary vibration characteristics. The frequency responses are presented to examine how the subsidiary resonance is altered for various situations of having different thickness of a yoke and permanent magnet and of having a different magnet circuit. Finally, the design guidelines to avoid the subsidiary resonance will be presented.

• 한국지구물리탐사학회:학술대회논문집
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• 2003.11a
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• pp.504-510
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• 2003

This study has been carried out to evaluate the passive treatment systems for acid mine drainage in Korea and to suggest, if possible, the method for the improvement. 35 passive treatment systems in 27 mines have been constructed since 1996. SAPS, being the main process, was combined with more than one of processes such as anaerobic wetland, aerobic wetland, and oxidation pond for the construction of passive treatment system. Problems observed during the operation include the poor sulfate removal ratio, overflow, leakage, unusabless of the whole system, and inefficiency. The reasons of the poor sulfate removal ratio are believed that the low temperature during the winter prohibits the SRB activity and HRT for bacterial sulfate reduction is insufficient. An alternative method In Adit Sulfate Reducing System which enables to keep the temperature constant at about $15^{\circ}C$ was suggested. IASRS is the methods of placing the SAPS inside the adit, which enables the temperature around the system constant can be maintained. The experiments using the laboratory scaled model systems made up of four sections showed high efficiencies in pH control and metal removal ratios, but showed still low sulfate removal ratio of about $23\%$ also with high COD at the beginning of the operation.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.87-95
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• 2016

Nonvolatile memory (NVM) is being considered as an alternative of traditional memory devices such as SRAM and DRAM, which suffer from various limitations due to the technology scaling of modern integrated circuits. Although NVMs have advantages including nonvolatility, low leakage current, and high density, their inferior write performance in terms of energy and endurance becomes a major challenge to the successful design of NVM-based memory systems. In order to overcome the aforementioned drawback of the NVM, extensive research is required to develop energy- and endurance-aware optimization techniques for NVM-based memory systems. However, researchers have experienced difficulty in finding a suitable simulation tool to prototype and evaluate new NVM optimization schemes because existing simulation tools do not consider the feature of NVM devices. In this article, we introduce a NVM-based cache simulator to support rapid prototyping and evaluation of NVM-based caches, as well as energy- and endurance-aware NVM cache optimization schemes. We demonstrate that the proposed NVM cache simulator can easily prototype PRAM cache and PRAM+STT-RAM hybrid cache as well as evaluate various write traffic reduction schemes and wear leveling schemes.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.451-453
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• 2007

This paper describes the design of an asynchronous implementation of a sensor network processor. The main purpose of this work is the reduction of power consumption in sensor network node processors and the research presented here tries to explore the suitability of asynchronous circuits for this purpose. The Handshake Solutions toolkit is used to implement an asynchronous version of a sensor processor. The design is made compact, trading area and leakage power savings with dynamic power costs, targeting the typical sparse operating characteristics of sensor node processors. It is then compared with a synchronous version of the same processor. Both versions are then compared with existing commercial processors in terms of power consumption.

• Applied Science and Convergence Technology
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• v.26 no.5
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• pp.133-138
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• 2017

We investigated the interface defect engineering and reaction mechanism of reduced transition layer and nitride layer in the active plasma process on 4H-SiC by the plasma reaction with the rapid processing time at the room temperature. Through the combination of experiment and theoretical studies, we clearly observed that advanced active plasma process on 4H-SiC of oxidation and nitridation have improved electrical properties by the stable bond structure and decrease of the interfacial defects. In the plasma oxidation system, we showed that plasma oxide on SiC has enhanced electrical characteristics than the thermally oxidation and suppressed generation of the interface trap density. The decrease of the defect states in transition layer and stress induced leakage current (SILC) clearly showed that plasma process enhances quality of $SiO_2$ by the reduction of transition layer due to the controlled interstitial C atoms. And in another processes, the Plasma Nitridation (PN) system, we investigated the modification in bond structure in the nitride SiC surface by the rapid PN process. We observed that converted N reacted through spontaneous incorporation the SiC sub-surface, resulting in N atoms converted to C-site by the low bond energy. In particular, electrical properties exhibited that the generated trap states was suppressed with the nitrided layer. The results of active plasma oxidation and nitridation system suggest plasma processes on SiC of rapid and low temperature process, compare with the traditional gas annealing process with high temperature and long process time.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.58.1-58.1
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• 2010

We have developed a novel crystallization process, where the crystallization temperature is lowered compared to the conventional RTA process and the metal contamination is lowered compared to the conventional VIC process. A very-thin a-Si film was deposited and crystallized at $550^{\circ}C$ for 3 h by the VIC process and then a thick a-Si film was deposited and crystallized by the RTA process at $680^{\circ}C$ for 5 min using the VIC poly-Si layer as a crystallization seed layer. The RTA crystallized temperature could be lowered up to $50^{\circ}C$, compared to RTA process alone. The poly-Si film appeared a needle-like growth front and relatively well-arranged (111) orientation. In addition, the Ni concentration in the poly-Si film was lowered to $3{\times}10^{17}\;cm^{-3}$ and that at the poly-Si/$SiO_2$ interface was lowered to $5{\times}10^{19}\;cm^{-3}$. The reduction in metal contamination could be greatly helpful to achieve a low leakage current in poly-Si TFT, which is the critical parameter for commercialization of AMOLED.

• Journal of Power Electronics
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• v.11 no.1
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• pp.97-104
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• 2011

This paper proposes a new alternating current driving method for highly capacitive loads such as plasma display panels or piezoelectric actuators, etc. In the proposed scheme, a current balance transformer, which has two windings with the same turn-ratio, provides not only a resonance inductance for energy recovery but also a current balance among all of the switching devices of the driver for current stress reduction. The smaller conduction loss than conventional circuits occurs due to the dual conduction paths which are parallel each other in the current balance transformer. Also, the leakage inductances of the transformer are utilized as resonant inductors for energy recovery by the series resonance to the capacitive load. Furthermore, the resonance contributes to the small switching losses of the switching devices by soft-switching operation. To confirm the validity of the proposed circuit, prototype hardware with a 12-inch mercury-free flat fluorescent lamp is implemented. The experimental results are compared with a conventional energy-recovery circuit from the perspective of luminance performances.