• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.1
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• pp.48-59
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• 1992

This paper presents the design of a layout processing system that performs circuit and symbolic extraction from hierarchical designs containing arbitrarily shaped layout. The system is flexible enough to deal with various technologies, MOS or bipolar, by providing extraction rules in the form of technology files. In this paper, new efficient algorithms for trapezoidal decomposition of polygon and symbolic path extraction using trapezoidal template are proposed for symbolic extraction. Circuit and symbolic extractor is developed as an integrated design environment of SOLID system.

• International Journal of Contents
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• v.1 no.2
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• pp.5-9
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• 2005

Currently most Internet documents including data are made based on predefined templates, but templates are usually formed only for main data and are not helpful for information retrieval against indexes, advertisements, header data etc. Templates in such forms are not appropriate when Internet documents are used as data for information retrieval. In order to process Internet documents in various areas of information retrieval, it is necessary to detect additional information such as advertisements and page indexes. Thus this study proposes a method of detecting the layout of Web pages by identifying the characteristics and structure of block tags that affect the layout of Web pages and calculating distances between Web pages. This method is purposed to reduce the cost of Web document automatic processing and improve processing efficiency by providing information about the structure of Web pages using templates through applying the method to information retrieval such as data extraction.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.9
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• pp.259-269
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• 2012

With the lower supply voltage and the higher operating frequency in integrated circuits, the analysis of the power distribution network (PDN) including on-chip inductances becomes more important. In this paper, an effective inductance extraction method for a regular on-chip power grid structure is proposed. The loop inductance model applicable to chip layout is proposed and the inductance extraction tool using the proposed inductance model based on post layout RC circuits is developed. The accuracy of the proposed loop model and the developed tool is verified by comparing the test circuit simulation results with those from the partial element equivalent circuit (PEEC) model. The voltage fluctuation from the RLC circuits extracted by the developed tool was examined for the analysis of on-chip inductance effects. The significance of on-chip power grid inductance was investigated by the co-simulation of chip-package-PCB.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.246-249
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• 2000

In this paper, we describe an automated extraction program that transforms a mask layout into an approximated equivalent circuit information suitable for circuit simulation, and that extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. To extract equivalent circuit from mask layout, we propose new block disassembly technique capable of accurate computations of distributed RCs at branch point, using vectorized edges which represent the outline of an individual polygon.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.113-116
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• 2001

In this paper we present a new hierarchical layout object extraction algorithm, which is based on rectangles rather than edges. The original layout data is modeled as instances connected by wires. Each polygon shape is divided into a set of rectangles and the instances and wires are extracted and recognized from those rectangles together with their connection and size information. We have applied the algorithm to actual layouts. Experiments on several standard cell library demonstrate the effectiveness of the algorithm.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.9
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• pp.46-58
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• 1993

Owing to the nature of locality in mask layouts, it appears that most mask layout problems can be solved by transforming a part of the given mask layout into a better layout segment continuously toward a global suboptimal solution. This notion of local transformation addresses major weak points of existing mask layout processing systems, which lack both extensibility and unifiability. This paper attempts to elaborate upon developing a new rule-based mask layout transformation system wherein most of the mask layout problems can be solved under the unified framework of local mask layout transformation. The rule-based mask layout transformation system is applicable to various mask layout problems such as net extraction, mask layout compaction, mask layout editing, and design rule checking. The experimental results show that the rule-based expert system approach is an efficient means of solving those mask layout problems, and thus confronting major drawbacks of existing layout processing systems.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.120-126
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• 1989

IC chip layout pattern recognition algorithms using image processing techniques are being developed for the automation of manufacturing and inspecting chips. Recognitioin of chip pattern requires feature extraction from nach rrame of chip image adn needs to match the feature data through all frames. In this paper, vertex position and form having layout information are extracted by the feature straightening algorithm, and global coordinates of layout pattern are extracted by the feature straightening algorithm, and global coordinates of layout pattern are obtainnd by vertex form matching from the overlapped area of neighbour frame.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.1976-1979
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• 2002

A new and efficient layout object extraction technique is presented in this paper, which is to be used in technology migration or hard-U reuse. The technique models the original polygon layout represented by a set of edges as a set of connected or overlapped rectangles. The rectangle model provides easy and efficient recognition, extraction, resizing, and compaction of layout objects such as transistors, contacts, and wires. Experiments on several designs from simple standard cells to more complex designs using standard and/or custom cells demonstrate the effectiveness of our technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.10
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• pp.1131-1146
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• 1992

In this paper, we suggest a new algorithm applied to the segmentation of published documents to obtain constituent and layout information of document. Firstly, we begin the process of blocking and labeling on a 300dpi scanned document. Secondly, we classify the blocked document by individual sub-regions. Thirdly, we group sub-regions into graphic areas and text areas. Finally, we extract information for layout recognition by using the data. From an experiment on papers of an academic society, we obtain the above 98% of region classification rate and extraction rate of information for the layout recognition.

• The Journal of the Korea Contents Association
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• v.5 no.4
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• pp.237-244
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• 2005

Currently most Internet documents including news data are made based on predefined templates, but templates are usually formed only for main data and are not helpful for information retrieval against indexes, advertisements, header data etc. Templates in such forms are not appropriate when Internet documents are used as data for information retrieval. In order to process Internet documents in various areas of information retrieval, it is necessary to detect additional information such as advertisements and page indexes. Thus this study proposes a method of detecting the layout of web pages by identifying the characteristics and structure of block tags that affect the layout of web pages and calculating distances between web pages. As a result of experiment, we can successfully extract 640 documents from 1000 samples and obtain 64% recall rate. This method is purposed to reduce the cost of web document automatic processing and improve its efficiency through applying the method to document preprocessing of information retrieval such as data extraction and document summarization.