• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.6 no.3
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• pp.168-173
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• 2013

In this paper, we tried different two approach to improve the performance of the IGBT. The first approach is that adding N+ region beside P-base in the conventional IGBT. It can make the conventional IGBT to get faster turn-off time and lower conduction loss. The second approach is that adding P+ region on right side under gate to improve latching current of conventional IGBT. The device simulation results show improved on-state, latch-up and switching characteristics in each structure. The first one was presented lower voltage drop(3.08V) and faster turn-off time(3.4us) than that of conventional one(3.66V/3.65us). Also, second structure has higher latching current(369A/?? ) that of conventional structure. Finally, we present a novel IGBT combined the first approach with second one for improved trade-off characteristic between conduction and turn-off losses. The proposed device has better performance than conventional IGBT.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of IKEEE
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• v.11 no.1 s.20
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• pp.69-76
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• 2007

This paper presents the design of LVDS (Low-Voltage-Differential-Signaling) transmitter for Gb/s-per-pin operation. The proposed LVDS transmitter is designed using BiCMOS technology, which can be compatible with CMOS technology. To reduce chip area and enhance the robustness of LVDS transmitter, the MOS switches of transmitter are replaced with lateral bipolar transistor. The common emitter current gain($\beta$) of designed bipolar transistor is 20 and the cell size of LVDS transmitter is $0.01mm^2$. Also the proposed LVDS driver is operated at 1.8V and the maximum data rate is 2.8Gb/s approximately In addition, a novel ESD protection circuit is designed to protect the ESD phenomenon. This structure has low latch-up phenomenon by using turn on/off character of P-channel MOSFET and low triggering voltage by N-channel MOSFET in the SCR structure. The triggering voltage and holding voltage are simulated to 2.2V, 1.1V respectively.

• Journal of IKEEE
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• v.20 no.4
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• pp.361-366
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• 2016

This paper presents the ESD protection circuit with improved electrical characteristic and area efficiency. The proposed ESD protection circuit has higher holding voltage and lower trigger voltage characteristics than the 3-Stacking LVTSCR. In addition, it has only two stages and has improved Ron characteristics due to short discharge path of ESD current. We analyzed the electrical characteristics of the proposed ESD protection circuit by TCAD simulator. The proposed ESD protection circuit has a small area of about 35% compared with 3-Stacking LVTSCR, The proposed circuit is designed to have improved latch-up immunity by setting the effective base length of two NPN parasitic bipolar transistors as a variable.

• Journal of Convergence for Information Technology
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• v.11 no.6
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• pp.7-13
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• 2021

In this paper, the function of starting the negative voltage used in the IT equipment when it is generated and the method of controlling it using a microcontroller for the function to detect the overload and respond to it are presented. To do this, the limitations of the existing negative voltage generation circuit and the problems that occur during overload were analyzed, and a circuit that detects and controls the overload condition without a separate current sensing circuit was presented. In order to confirm the effect of the proposed method, an experiment was conducted by configuring an experimental circuit. As a result of the experiment, compared to the existing negative voltage generation circuit, which falls into a latch-up state when overloaded and enters a dangerous state, the proposed circuit detects this, stop the operation of the circuit, and informs the user of such an abnormal state to take action. have. In addition, since the starting point of the circuit is determined according to the system state, the experimental result was confirmed that the starting time was significantly shortened by about 23% compared to the time switch method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.30 no.9
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• pp.535-540
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• 2017

The changes in the electrical characteristics of CMOS ICs due to coupling with a narrow-band electromagnetic wave were analyzed in this study. A magnetron (3 kW, 2.45 GHz) was used as the narrow-band electromagnetic source. The DUT was a CMOS logic IC and the gate output was in the ON state. The malfunction of the ICs was confirmed by monitoring the variation of the gate output voltage. It was observed that malfunction (self-reset) and destruction of the ICs occurred as the electric field increased. To confirm the variation of electrical characteristics of the ICs due to the narrow-band electromagnetic wave, the pin-to-pin resistances (Vcc-GND, Vcc-Input1, Input1-GND) and input capacitance of the ICs were measured. The pin-to-pin resistances and input capacitance of the ICs before exposure to the narrow-band electromagnetic waves were $8.57M{\Omega}$ (Vcc-GND), $14.14M{\Omega}$ (Vcc-Input1), $18.24M{\Omega}$ (Input1-GND), and 5 pF (input capacitance). The ICs exposed to narrow-band electromagnetic waves showed mostly similar values, but some error values were observed, such as $2.5{\Omega}$, $50M{\Omega}$, or 71 pF. This is attributed to the breakdown of the pn junction when latch-up in CMOS occurred. In order to confirm surface damage of the ICs, the epoxy molding compound was removed and then studied with an optical microscope. In general, there was severe deterioration in the PCB trace. It is considered that the current density of the trace increased due to the electromagnetic wave, resulting in the deterioration of the trace. The results of this study can be applied as basic data for the analysis of the effect of narrow-band high-power electromagnetic waves on ICs.