• Title/Summary/Keyword: Latch

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Structural Stability Analysis of Connectors for an Electric Handbike (휠체어 전동주행 보조기기용 커넥터의 구조안정성 해석)

  • Seo, Han Wool;Kim, Dae Dong;Ko, Cheol Woong;Lee, Joon Hmm;Bae, Tae Soo
    • Journal of the Korean Society for Precision Engineering
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    • v.32 no.5
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    • pp.491-496
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    • 2015
  • Electric handbike can be easily detachable to various sizes of manual wheelchair and the elderly and people with disabilities can use them easily. Therefore, connectors used for coupling between the handbike and manual wheelchair must secure structural stability for occupant safety. However, related research is rare. The aim of this study is to find the connector with highly structural stability by comparing static and dynamic mechanical characteristics among three typical connectors(a snatch lock, a slide latch, and a fastener) by computational simulations. To perform static and dynamic simulation, we referred to durability test based on Korean Standards and then calculated mechanical stresses in connectors. The results showed that the snatch lock addressed the lowest von-mises stress under the same mechanical condition. Therefore when using the combination of a handbike and a wheelchair, we concluded that the snatch lock is considered as the structurally stable connector to structural stability and usability.

Design of 3V a Low-Power CMOS Analog-to-Digital Converter (3V 저전력 CMOS 아날로그-디지털 변환기 설계)

  • 조성익;최경진;신홍규
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.11
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    • pp.10-17
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    • 1999
  • In this paper, CMOS IADC(Current-mode Analog-to-Digital Converter) which consists of only CMOS transistors is proposed. Each stages is made up 1.5-bit bit cells composed of CSH(Current-mode Sample-and-Hold) and CCMP(Current Comparator). The differential CSH which designed to eliminate CFT(Clock Feedthrough), to meet at least 9-bit resolution, is placed at the front-end of each bit cells, and each stages of bit cell ADSC (Analog-to-Digital Subconverter) is made up two latch CCMPs. With the HYUNDAI TEX>$0.65\mu\textrm{m}$ CMOS parameter, the ACAD simulation results show that the proposed IADC can be operated with 47 dB of SINAD(Signal to Noise- Plus-Distortion), 50dB(8-bit) of SNR(Signal-to-Noise) and 37.7 mW of power consumption for input signal of 100 KHz at 20 Ms/s.

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A 1-V 1.6-GS/s 5.58-ENOB CMOS Flash ADC using Time-Domain Comparator

  • Lee, Han-Yeol;Jeong, Dong-Gil;Hwang, Yu-Jeong;Lee, Hyun-Bae;Jang, Young-Chan
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.695-702
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    • 2015
  • A 1-V 1.6-GS/s 5.58-ENOB flash ADC with a high-speed time-domain comparator is proposed. The proposed time-domain comparator, which consumes low power, improves the comparison capability in high-speed operations and results in the removal of preamplifiers from the first-stage of the flash ADC. The time interpolation with two factors, implemented using the proposed time-domain comparator array and SR latch array, reduces the area and power consumption. The proposed flash ADC has been implemented using a 65-nm 1-poly 8-metal CMOS process with a 1-V supply voltage. The measured DNL and INL are 0.28 and 0.41 LSB, respectively. The SNDR is measured to be 35.37 dB at the Nyquist frequency. The FoM and chip area of the flash ADC are 0.38 pJ/c-s and $620{\times}340{\mu}m^2$, respectively.

Cathode Side Engineering to Raise Holding Voltage of SCR in a 0.5-㎛ 24 V CDMOS Process

  • Wang, Yang;Jin, Xiangliang;Zhou, Acheng;Yang, Liu
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.6
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    • pp.601-607
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    • 2015
  • A set of novel silicon controlled rectifier (SCR) devices' characteristics have been analyzed and verified under the electrostatic discharge (ESD) stress. A ring-shaped diffusion was added to their anode or cathode in order to improve the holding voltage (Vh) of SCR structure by creating new current discharging path and decreasing the emitter injection efficiency (${\gamma}$) of parasitic Bipolar Junction Transistor (BJT). ESD current density distribution imitated by 2-dimensional (2D) TCAD simulation demonstrated that an additional current path exists in the proposed SCR. All the related devices were investigated and characterized based on transmission line pulse (TLP) test system in a standard $0.5-{\mu}m$ 24 V CDMOS process. The proposed SCR devices with ring-shaped anode (RASCR) and ring-shaped cathode (RCSCR) own higher Vh than that of Simple SCR (S_SCR). Especially, the Vh of RCSCR has been raised above 33 V. What's more, their holding current is kept over 800 mA, which makes it possible to design power clamp with SCR structure for on chip ESD protection and keep the protected chip away from latch-up risk.

Concept Analysis of Effective Breastfeeding (효과적인 모유수유 개념 분석)

  • Yang, Huyn-Joo;Seo, Ji-Min
    • Women's Health Nursing
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    • v.17 no.4
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    • pp.317-327
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    • 2011
  • Purpose: This study was conducted to analyze and clarify the concept of the effective breastfeeding. Methods: This study used Walker and Avant's process of concept analysis. Results: Effective breastfeeding is how to give infant adequate milk, which fulfills needs of mother and infant, from her breast so that they can be satisfied with the process and results. It included the effective breastfeeding properties as follows: feeding behaviors (positioning, latch on, and suckling), transferring a breast milk to an infant, mother-infant interaction, and satisfying their desires (satisfaction, comfort, mother's self-confidence, infant's adequate weight gain and defecation, adequate breastfeeding interval). The antecedent of effective breastfeeding were anatomical and functional normal breast, breastfeeding knowledge and steady-state of mother, and feeding desire, rooting reflex and normal oral cavity of infant. The consequences of effective breastfeeding were exclusive breastfeeding, infant and maternal health and wellbeing, and achievement of mother and infant attachment. Conclusion: The meaning of effective breastfeeding defined in this study will contribute to develop the effectiveness breastfeeding assessment tool and the nursing intervention for ineffective breastfeeding.

Design of Advanced Successive Approximation A/D Converter for High-Speed, Low-Resolution, Low-Cost, Low-Power Application (고속, 저해상도, 저비용, 저전력용 Successive Approximation A/D 변환기의 설계)

  • Kim, Sung-Mook;Chung, Kang-Min
    • Proceedings of the Korea Information Processing Society Conference
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    • 2005.05a
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    • pp.1765-1768
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    • 2005
  • Binary-search 알고리즘을 이용한 새로운 6-bit 300MS/s ADC 를 제안 하였다. 본 연구에서 제안된 ADC 는 저전력, 고속동작, 저해상도의 응용분야에 적합하도록 설계 되었다. 11 개의 rail-to-rail 비교기와 기준전압 발생기, 그리고 기준전압 제어회로로 구성 되었으며, 이는 기존의 구조와는 다른 전혀 새로운 형태로 제안된 것이다. 전력소모를 줄이기 위해 비교기 공유기술을 사용하였다. 또한 ADC 의 sub-block 인 rail-to-rail 비교기는 인버터 logic threshold 전압 값을 이용한 새로운 형태의 비교기를 제안하였다. 비교기는 인버터와 n-type preamp, p-type preamp 그리고 각각에 연결되는 latch 로 구성되었다. 기존의 rail-to-rail comparator 에 비해 입력 범위 전체 영역에서 일정한 gm 값을 얻을 수 있다. 실험결과 2.5V 공급전압에서, 17mW 의 전력 소모를 보이며, 최대 304MS/s 의 데이터 변환율을 가진다. INL 과 DNL 은 입력신호가 2.38Mhz 의 주파수를 가지는 삼각파일 때, 각각 ${\pm}0.54LSB$, ${\pm}1LSB$ 보다 작다. TSMC 0.25u 공정을 이용하였다.

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Fabrication of Micro-optical Components and Actuators using Surface Micromachining (표면 미세가공기술을 이용한 마이크로 광학소자 및 구동기의 제작)

  • Kim, K.N.;Park, K.B.;Jung, S.W.;Lee, B.N.;Kim, I.H.;Moon, H.C.;Park, H.D.;Shin, S.M.
    • Proceedings of the KIEE Conference
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    • 1999.11d
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    • pp.1151-1153
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    • 1999
  • 3-layer polysilicon 표면미세가공공정을 이용하여 micro zone plate 렌즈와 미러 및 이를 구동하기 위한 구동기를 일체화시킨 마이크로 구동형 광학소자를 설계, 제작하였다. 650nm의 파장대역에서 초점거리가 $500{\mu}m$가 되도록 마이크로 zone plate 렌즈를 설계하였으며, 렌즈의 광학축은 실리콘 기판 상에서 $121{\mu}m$거리에 위치하도록 제작하였다. 마이크로 hinge와 스프링 latch 및 측면지지 plate를 이용하여 마이크로 렌즈와 미러가 실리콘 기판상에서 out-of-plane동작이 가능하도록 하였다. 마이크로렌즈 초점거리의 가변을 위하여 6개의 SDA(Scratch Drive Actuator)어레이를 설계, 제작하였다. 또한 빔 반사를 위한 마이크로 미러를 설계하고 $45^{\circ}$ self-assembly를 위하여 마이크로 hinge와 SDA array를 제작하였다.

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A Study on the Design of the LIGBT Structure with Trap Injection for Improved Electrical Characteristics (트랩 주입의 구조적 설계에 따른 LIGBT의 전기적 특성 개선에 관한 연구)

  • Choo, Kyo-Hyuck;Kang, Ey-Goo;Lee, Jung-Hoon;Sung, Man-Young
    • Proceedings of the KIEE Conference
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    • 1999.11d
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    • pp.932-934
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    • 1999
  • In this paper, the new IGBT structures with trap injection are proposed to improve switching characteristics of the conventional SOI LIGBT. The simulations are used in order to investigate the effects of the position, width and concentration of trap injection region using 2D device simulator MEDICI. And, their electrical characteristics are analyze and the optimum design parameters are extracted. As a result of simulation, the turn off time for the proposed LIGBT model A by the trap injection is $0.78{\mu}s$. And, the latch up voltage is 3.4V and forward blocking voltage is 168V which are superior to that of conventional structure. In addition, the proposed model is achieved more efficient in switching time and process effort. Therefore, It is shown that the trap injection is very effective to reduce the turn off time with a little increasing of on-state voltage drop if its design and process parameters are optimized.

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Development of Gas Production Measurement System by Bubble Counting during Fermentation (기포계수식 발효가스 발생량 계측시스템의 개발)

  • Lee, Young-Jin;Chun, Jae-Kun
    • Korean Journal of Food Science and Technology
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    • v.26 no.3
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    • pp.195-198
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    • 1994
  • A bubble counter was designed and fabricated for the measurement of gas production rate on the basis of number of bubbles produced from yeast fermentor. The sensor was consisted of bubble forming device and electronic signal processing circuitry. The bubble forming device was built with bubble collector and liquid cell to form uniform size of bubble. Bubbles were counted by pulses formed by photo-interrupter circuitry having 8-bit binary latch counter. The gas production rate curves on the basis of bubble counted showed a good agreement to that of growth curves obtained by the optical measurement method. The sensor was succesfully applied to monitoring of the nutrient utilization test with glucose and galactose media.

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Characteristic Study for Defect of Top Si and Buried Oxide Layer on the Bonded SOI Wafer (Bonded SOI wafer의 top Si과 buried oxide layer의 결함에 대한 연구)

  • Kim Suk-Goo;Paik Un-gyu;Park Jea-Gun
    • Korean Journal of Materials Research
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    • v.14 no.6
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    • pp.413-419
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    • 2004
  • Recently, Silicon On Insulator (SOI) devices emerged to achieve better device characteristics such as higher operation speed, lower power consumption and latch-up immunity. Nevertheless, there are many detrimental defects in SOI wafers such as hydrofluoric-acid (HF)-defects, pinhole, islands, threading dislocations (TD), pyramid stacking faults (PSF), and surface roughness originating from quality of buried oxide film layer. Although the number of defects in SOI wafers has been greatly reduced over the past decade, the turn over of high-speed microprocessors using SOI wafers has been delayed because of unknown defects in SOI wafers. A new characterization method is proposed to investigate the crystalline quality, the buried oxide integrity and some electrical parameters of bonded SOI wafers. In this study, major surface defects in bonded SOI are reviewed using HF dipping, Secco etching, Cu-decoration followed by focused ion beam (FIB) and transmission electron microscope (TEM).