• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.951-954
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• 2003

본 논문에서는 고속. 저전력에 적합한 개방 구조를 갖는 8-비트 500Msmaples/s 2-Step ADC 를 제안하였다. 500Msmaples/s 의 고속 동작을 위해서 기존의 M-DAC을 이용한 폐쇄 구조 대신 개방형 구조를 사용하였다. 이와 더불어 저전력을 구현하기 위해서 analog-latch 를 제안하여 동적 동작을 수행시킴으로써 전력 소모를 줄였으며 , mux 의 구현 시 reset switch를 이용하여 로딩 시간을 개선함으로써 high-speed 에 적합하도록 설계하였다. 제안된 ADC 는 1-poly 6-metal 0.18um CMOS 공정을 이용하였으며 1.8V 전원 전압을 이용하여 250mW 의 전력을 소모하며 500M 샘플링 주파수에서 120MHz 신호 입력 시 7.6 비트의 ENOB를 얻을 수 있었다.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.863-866
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• 2003

Recently, there has been growing interests in the magneto-resistive random access memory (MRAM) because of its great potential as a future nonvolatile memory. In this paper, a CMOS macro-model for MRAM cell based on a twin cell structure is proposed. The READ and WRITE operations of the MTJ cell can be emulated by adopting data latch and switch blocks. The behavior of the circuit is confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process. We expect the macro model can be utilized to develope the core architecture and the peripheral circuitry. It can also be used for the characterization and the direction of the real MTJ cells.

• The Magazine of the IEIE
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• v.24 no.6
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• pp.38-49
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• 1997

0.4mm Resign Rule의 Super Low Power Dissipation, Low Voltage. Operation-5- Full CMOS SRAM Cell을 개발하였다. Retrograde Well과 PSL(Poly Spacer LOCOS) Isolation 공정을 사용하여 1.76mm의 n+/p+ Isolation을 구현하였으며 Ti/TiN Local Interconnection을 사용하여 Polycide수준의 Rs와 작은 Contact저항을 확보하였다. p-well내의 Boron이 Field oxide에 침적되어 n+/n-well Isolation이 취약해짐을 Simulation을 통해 확인할 수 있었으며, 기생 Lateral NPN Bipolar Transistor의 Latch Up 특성이 취약해 지는 n+/n-wellslze는 0.57mm이고, 기생 Vertical PNP Bipolar Transistor는 p+/p-well size 0.52mm까지 안정적인 Current Gain을 유지함을 알 수 있었다. Ti/TiN Local Interconnection의 Rs를 Polycide 수준으로 낮추는 것은 TiN deco시 Power를 증가시키고 Pressure를 감소시킴으로써 실현할 수 있었다. Static Noise Margin분석을 통해 Vcc 0.6V에서도 Cell의 동작 Margin이 있음을 확인할 수 있었으며, Load Device의 큰 전류로 Soft Error를 개선할수 있었다. 본 공정으로 제조한 1M Full CMOS SRAM에서 Low Vcc margin 1.0V, Stand-by current 1mA이하(Vcc=3.7V, 85℃기준) 를 얻을 수 있었다.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.25 no.3
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• pp.362-368
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• 2001

To design a limiting MCCB (Molded Case Circuit Breaker) mechanism, a dynamic modeling of the mechanism in which the electro-magnetic force effects are incorporated needs to be developed. Conventionally, electro-magnetic effects were considered separately for the design of the mechanism. In this paper, an electro-magnetic force that is induced by limited current is identified and included in the dynamic modeling of the mechanism. Thus, the electro-magnetic which is defined as a external force and the mechanical effects are simultaneously considered for the design of the mechanism which is composed of contactor, spring , link, latch and so on.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.901-909
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• 1990

With a wide spread of 32 bit personal computers, a simple structure and high performance memory system have been highly required. In this paper, a memory block is constructed by using a modified hierarchical bit line in which the DRAM bit line and the latch which works as a SRAM cell are integrated by an interface gate. And the new architecture memory DSRAM(Dynamic Static RAM) is proposed by interleaving the 16 memory block. Because the DSRAM works with 16 page, the page is miss ratio becomes small and the RAS precharge time which is incurred by page miss is shortened. So the DSRAM can implement an optimum page interleaving and it has good compatibility to the existing DRAMs. The DSRAM can be widely used in small computers as well as a high performance memory system.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.137-140
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• 2001

This paper shows an asynchronous comparator circuit for 1.2Gbps signal receiver that converts 1.2Gbps data rate input signals with less than 100㎷ swing to on-chip CMOS compatible voltage levels in a 0.35${\mu}{\textrm}{m}$ CMOS process. Folded-cascode nMOS input stage with source-coupled pMOS input stage cover rail-to-rail input common-mode range. Drastic gain-bandwidth increment due to gain-boosting stage with positive-feedback latch as well as wide input common-mode range make designed circuit be suitable for a fully differential signal receiver. HSPICE simulation results show that worst-case sensitivity is less than 20㎷ and maximum propagation delay is 640-psec. And also we verified 3.97㎽ power consumption with 150㎷ differential swing amplitude at 1.2Gbps.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.9 s.240
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• pp.1282-1288
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• 2005

This research has been motivated by the need to minimize possible leakage of microwave when one opens the door during operation of the microwave oven. An explicit finite element program is used to analyze the transient response the door of the oven under door-opening condition. Operation of the micro switch which plays an important role to hun off the power is simulated on the basis of the response of the latch. Using the results of the analysis, twisting deformation of the door frame is defined and evaluated.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1427-1432
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• 2008

This paper describes the locomotion of a water jumping robot which attempts to emulate the fishing spider’s ability to jump on the water surface. While previous studies of the robots mimicking arthropods living on water were focused on recreating their horizontal skating motions, here we aim to achieve a vertical jumping motion. The robot jumps by pushing the water surface with rapidly released legs which were initially bent. The motion is triggered with a latch driven by the shape memory alloy actuator. The robot is capable of jumping to the maximum height of 26mm. Jumping efficiency, defined the maximum jumping height on water over the maximum jumping height on rigid ground, is 0.26 This work represents a first step toward robots that can locomote on water with superior versatility including skating and jumping.

• 한국컴퓨터산업교육학회:학술대회논문집
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• 2003.11a
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• pp.67-70
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• 2003

In this paper, propose a new structure of MOFET(Metal-Oxide-Semiconductor Field Effect Transistor) which is widely application for semiconductor technologies. Eleminate the latch-up effect caused by closed devices when conpose a electronic circuit using proposed devices. In this device have a completely isolation structure, and advantage of leakage current elimination. Each independent devices are isolated by trench-well and oxide layer of SOI substrate. Using trench gate and self aligned techniques reduces parasitic capacitance between gate and source, drain. In this paper, we proposed the new structure of SOI MOSFET which has completely isolation and contains trench gate electrodes and SOI wafers. It is simulated by MEDICI that is device simulator.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.567-570
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• 2002

The LVDS (Low Voltage Differential Signaling) I/O cells, fully compatible with ANSI TIA/ EIA-644 LVDS standard, are designed using a 0.35${\mu}m$ standard CMOS technology. With a single 3V supply, the core cells operate at 1.34Gbps and power consumption of the output driver and the input receiver is 10. 5mW and 4.2mW, respectively. In the output driver, we employ the DCMFB (Dynamic Common-Mode FeedBack) circuit which can control the DC offset voltage of differential output signals. The SPICE simulation result of the proposed output driver shows that the variation of the DC offset voltage is 15.6% within a permissible range. In the input receiver, the proposed dual input stage with a positive feedback latch covers rail-to-rail input common-mode range and enables a high-speed, low-power operation. 5-channels of the proposed LVDS I/O pair can handle display data up to 8-bit gray scale and UXGA resolution.