• 대한음성학회:학술대회논문집
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• 대한음성학회 2005년도 춘계 학술대회 발표논문집
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• pp.3-7
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• 2005

This research is for finding prototypes and characteristics of intonation found in ${\ulcorner}$-a/e, $t{\int}ijo$<${\lrcorner}$ and ${\ulcorner}$p/simnida${\lrcorner}$ among modern Korean predicate statements by constructing spoken corpus based on the current radio broadcast. So the result of the study is as follows. : (1) The construction of the balanced spoken corpus and the standard for boundary determination of rhythm are needed for the intonation model of speech synthesis. (2) Korean intonation units have the splited word tone which includes the nuclear tone and the pre-nuclear tone makes unclear tone more detailed. (3) I made man and woman intonation models individually through t-test of SPSS. (4) The standard intonation model is devided '-ajo'type and '-nida'type

• 대한음성학회:학술대회논문집
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• 대한음성학회 2007년도 한국음성과학회 공동학술대회 발표논문집
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• pp.311-314
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• 2007

Spoken dialog system development includes many laborious and inefficient tasks. Since there are many components such as speech recognizer, language understanding, dialog management and knowledge management in a spoken dialog system, a developer should take an effort to edit corpus and train each model separately. To reduce a cost for editting corpus and training each models, we need more systematic and efficent working environment. For the working environment, we propose DialogStudio as an spoken dialog system workbench.

• 전자공학회논문지B
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• 제32B권5호
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• pp.798-811
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• 1995

In this study, radar data integrating and processing systems were designed for the data processing of various information from many kinds of radar in a single data processing system. The characteristics of the data integrating system were analyzed by the system simulation with the queueing theory. The designed data integrating systems can be divided into a centralized and a distributed type. In the system structure, we used UNIX message que as the real time processor and the queueing theory for the performance evaluation of the information flow in the systems. For the analysis of the performance of inforamtion flow in both models, queueing theory was applied to and implemented with the simulation package, OPNET system and C language. From the simulation result we could understand the system factors which effect the system performance and characteristics on the data processing.

• 전자공학회논문지A
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• 제33A권6호
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• pp.220-229
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• 1996

We presetn sytem-level simulation methodology as well as environment setup established for CDMA digtial cellular mobile station in an effort to verify CDMA modem ASIC design. To make the system-level simulation feasible, behavioral modeling of a microcontroller was first carried out with VHDL. In addition, models written in C language were also developed to provide ASIC with realistic input data. Finally, the netlist of CDMA modem ASIC was loaded on the a hardware accelerator, which was interfaced with VHDL simulator, and ismulation was performed by excuting the actual CDMA call processing software. Simulation resutls thus obtained were confirmed by comparing them with the emulation resutls from the actual system constructed on hardware modeler. these methods were proved to be effective in both discovering in advance malfunctions when embedded in the system or design errors of ASIC and reducing simulation time by a factor of as much as 20 in case of simulation at gate-level.

• 산업경영시스템학회지
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• 제29권3호
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• pp.111-118
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• 2006

This paper presents design and development of a simulator evaluates the performance of a hierarchical cellular system. The proposed hierarchical cellular simulator, consisting of macro, micro, and pico cells, applies the wrap-around technique to reduce simulation time. The simulator is implemented as object oriented class models by using the C++ language in a PC environment. The resulting application can evaluate the interference, SIR(Signal to Interference Ratio), and capacity of a hierarchical cellular system in various configurations. Moreover, it can be used in other applications such as power control, call admission control, hand over scheme.

• 대한전자공학회논문지
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• 제25권6호
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• pp.637-646
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• 1988

The CMOS physical parameters are extracted using by processing models in fabrication steps, processing parameters, fabrication disturbances, control parameters. Statistical CMOS process and device simulator is proposed to evaluate the effect of inherent fluctuations in IC fabrication. Using this simulator, we perform worst case analysis in terms of statistically independent disturbances and compare this proposed method to Monte Carlo method, previous Worst Case method. And simulation results with this proposed method are more accurate than the past worst case analysis. This package is written in C language and runs on a IBM PC AT(OPUS).

• 전자공학회논문지C
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• 제34C권8호
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• 한국전기전자재료학회논문지
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• 제26권5호
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• pp.341-346
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• 2013

Threshold voltage shift caused by trapping and release of charge carriers in a thin-film transistor (TFT) is implemented in AIM-SPICE tool. Turning on and off voltages are alternatively applied to a TFT to extract charge trapping and releasing process. Each process is divided into sequentially ordered processes, which are numerically modeled and implemented in a computer language. The results show a good agreement with the experimental data, which are modeled. Since the proposed method is independent of TFT's behavior models implemented in SPICE tools, it can be easily added to them.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.379-380
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• 2008

For proper application and operation of a SFCL(Superconducting Fault Current Limiter), the prior investigation of fundamental characteristics and its effects to the distribution systems are needed. In this paper, the resistive type SFCL and recloser were developed by using EMTP/ATPDraw and MODELS language. To analyze the effect of recovery characteristics of SFCL according to recloser operation in distribution systems, case studies have been simulated and investigated.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2008년도 제39회 하계학술대회
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• pp.381-382
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• 2008

This paper presents a novel scheme for reducing an asymmetry current with SFCL (Superconducting Fault Current Limiter) operation during transient period, when a fault occurs in power systems. The main idea is installation an auxiliary SFCL with characteristics, which reduces the asymmetry fault current in first half cycle before the operating of main SFCL. For proper activities of SFCLs, the principle of asymmetry current nature is reviewed. A scheme of asymmetry components reduction with SFCL is then explained. The EMTP/ATPDraw model of SFCLs using MODELS language developed and simulated to verify the performance and effectiveness.