• Title/Summary/Keyword: LUT

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VLSI Architecture of High Performance Huffman Codec (고성능 허프만 코덱의 VLSI 구조)

  • Choi, Hyun-Jun;Seo, Young-Ho;Kim, Dong-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.15 no.2
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    • pp.439-446
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    • 2011
  • In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz

A Study on the Estimation of the Sea Surface Temperature from AVHRR CH4 data of NOAA-9 (극궤도 기상위성 NOAA-9호의 AVHRR CH4 data로 부터 해수면온도 산출과정에 관한 연구)

  • 이희훈;서애숙
    • Korean Journal of Remote Sensing
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    • v.3 no.1
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    • pp.41-54
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    • 1987
  • Accurate determination of Sea Surface Temperature (SST) is essential for ocean and climate studies. This paper estimated SST in the sea region around the Korea from the Advenced Very High Resolution Radiometer(AVHRR) channel 4 data on board NOAA-9 satellite. The processing procedure used to derive SSTs utilized: 1) Ascending node prediction of satellite orbit 2) Geometric correction 3) Radiometric calibration and radiance to temperature conversion look up table 4) Removing cloudy area. SST product results are displayed as colored video and hardcopy. In this processing, geometric correction is derived from equator crossing time, ascending time and subpoint coordinate information. Also, normalized response function of infrared 10.5-11.5$\mu\textrm{m}$ wavelength is used for temperature conversion. The SST derived from this processing is relatively similar to the measurements made by ship data, but because of water vapor attenuation SST from satellite are in general 2$^{\circ}$- $^{\circ}C$ lower than the ship data.

Aerosol Optical Thickness Retrieval Using a Small Satellite

  • Wong, Man Sing;Lee, Kwon-Ho;Nichol, Janet;Kim, Young J.
    • Korean Journal of Remote Sensing
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    • v.26 no.6
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    • pp.605-615
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    • 2010
  • This study demonstrates the feasibility of small satellite, namely PROBA platform with the compact high resolution imaging spectrometer (CHRIS), for aerosol retrieval in Hong Kong. The rationale of our technique is to estimate the aerosol reflectances by decomposing the Top of Atmosphere (TOA) reflectances from surface reflectance and Rayleigh path reflectances. For the determination of surface reflectances, the modified Minimum Reflectance Technique (MRT) is used on three winter ortho-rectified CHRIS images: Dec-18-2005, Feb-07-2006, Nov-09-2006. For validation purpose, MRT image was compared with ground based multispectral radiometer measurements and atmospherically corrected Landsat image. Results show good agreements between CHRIS-derived surface reflectance and both by ground measurement data as well as by Landsat image (r>0.84). The Root-Mean-Square Errors (RMSE) at 485, 551 and 660nm are 0.99%, 1.19%, and 1.53%, respectively. For aerosol retrieval, Look Up Tables (LUT) which are aerosol reflectances as a function of various AOT values were calculated by SBDART code with AERONET inversion products. The CHRIS derived Aerosol Optical Thickness (AOT) images were then validated with AERONET sunphotometer measurements and the differences are 0.05~0.11 (error=10~18%) at 440nm wavelength. The errors are relatively small compared to those from the operational moderate resolution imaging spectroradiometer (MODIS) Deep Blue algorithm (within 30%) and MODIS ocean algorithm (within 20%).

A 521-bit high-performance modular multiplier using 3-way Toom-Cook multiplication and fast reduction algorithm (3-way Toom-Cook 곱셈과 고속 축약 알고리듬을 이용한 521-비트 고성능 모듈러 곱셈기)

  • Yang, Hyeon-Jun;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.25 no.12
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    • pp.1882-1889
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    • 2021
  • This paper describes a high-performance hardware implementation of modular multiplication used as a core operation in elliptic curve cryptography. A 521-bit high-performance modular multiplier for NIST P-521 curve was designed by adopting 3-way Toom-Cook integer multiplication and fast reduction algorithm. Considering the property of the 3-way Toom-Cook algorithm in which the result of integer multiplication is multiplied by 1/3, modular multiplication was implemented on the Toom-Cook domain where the operands were multiplied by 3. The modular multiplier was implemented in the xczu7ev FPGA device to verify its hardware operation, and hardware resources of 69,958 LUTs, 4,991 flip-flops, and 101 DSP blocks were used. The maximum operating frequency on the Zynq7 FPGA device was 50 MHz, and it was estimated that about 4.16 million modular multiplications per second could be achieved.

FPGA-Based Acceleration of Range Doppler Algorithm for Real-Time Synthetic Aperture Radar Imaging (실시간 SAR 영상 생성을 위한 Range Doppler 알고리즘의 FPGA 기반 가속화)

  • Jeong, Dongmin;Lee, Wookyung;Jung, Yunho
    • Journal of IKEEE
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    • v.25 no.4
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    • pp.634-643
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    • 2021
  • In this paper, an FPGA-based acceleration scheme of range Doppler algorithm (RDA) is proposed for the real time synthetic aperture radar (SAR) imaging. Hardware architectures of matched filter based on systolic array architecture and a high speed sinc interpolator to compensate range cell migration (RCM) are presented. In addition, the proposed hardware was implemented and accelerated on Xilinx Alveo FPGA. Experimental results for 4096×4096-size SAR imaging showed that FPGA-based implementation achieves 2 times acceleration compared to GPU-based design. It was also confirmed the proposed design can be implemented with 60,247 CLB LUTs, 103,728 CLB registers, 20 block RAM tiles and 592 DPSs at the operating frequency of 312 MHz.

The effect of UV-C irradiation and EDTA on the uptake of Co2+ by antimony oxide in the presence and absence of competing cations Ca2+ and Ni2+

  • Malinen, Leena;Repo, Eveliina;Harjula, Risto;Huittinen, Nina
    • Nuclear Engineering and Technology
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    • v.54 no.2
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    • pp.627-636
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    • 2022
  • In nuclear power plants and other nuclear facilities the removal of cobalt from radioactive liquid waste is needed to reduce the radioactivity concentration in effluents. In liquid wastes containing strong organic complexing agents such as EDTA cobalt removal can be problematic due to the high stability of the Co-EDTA complex. In this study, the removal of cobalt from NaNO3 solutions using antimony oxide (Sb2O3) synthesized from potassium hexahydroxoantimonate was investigated in the absence and presence of EDTA. The uptake studies on the ion exchange material were conducted both in the dark (absence of UV-light) and under UV-C irradiation. Ca2+ or Ni2+ were included in the experiments as competing cations to test the selectivity of the ion exchanger. Results show that UV-C irradiation noticeably enhances the cobalt sorption efficiency on the antimony oxide. It was shown that nickel decreased the sorption of cobalt to a higher extent than calcium. Finally, the sorption data collected for Co2+ on antimony oxide was modeled using six different isotherm models. The Sips model was found to be the most suitable model to describe the sorption process. The Dubinin-Radushkevich model was further used to calculate the adsorption energy, which was found to be 6.2 kJ mol-1.

A High-Performance ECC Processor Supporting NIST P-521 Elliptic Curve (NIST P-521 타원곡선을 지원하는 고성능 ECC 프로세서)

  • Yang, Hyeon-Jun;Shin, Kyung-Wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.4
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    • pp.548-555
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    • 2022
  • This paper describes the hardware implementation of elliptic curve cryptography (ECC) used as a core operation in elliptic curve digital signature algorithm (ECDSA). The ECC processor supports eight operation modes (four point operations, four modular operations) on the NIST P-521 curve. In order to minimize computation complexity required for point scalar multiplication (PSM), the radix-4 Booth encoding scheme and modified Jacobian coordinate system were adopted, which was based on the complexity analysis for five PSM algorithms and four different coordinate systems. Modular multiplication was implemented using a modified 3-Way Toom-Cook multiplication and a modified fast reduction algorithm. The ECC processor was implemented on xczu7ev FPGA device to verify hardware operation. Hardware resources of 101,921 LUTs, 18,357 flip-flops and 101 DSP blocks were used, and it was evaluated that about 370 PSM operations per second were achieved at a maximum operation clock frequency of 45 MHz.

Design and Evaluation of 32-Bit RISC-V Processor Using FPGA (FPGA를 이용한 32-Bit RISC-V 프로세서 설계 및 평가)

  • Jang, Sungyeong;Park, Sangwoo;Kwon, Guyun;Suh, Taeweon
    • KIPS Transactions on Computer and Communication Systems
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    • v.11 no.1
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    • pp.1-8
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    • 2022
  • RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.

Natural Regeneration Potential of the Soil Seed Bank of Land Use Types in Ecosystems of Ogun River Watershed

  • Asinwa, Israel Olatunji;Olajuyigbe, Samuel Olalekan
    • Journal of Forest and Environmental Science
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    • v.38 no.3
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    • pp.141-151
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    • 2022
  • Soil seed banks as natural storage of plant seeds play an important role in the maintenance and regeneration of watershed. Natural regeneration potential of the soil seed bank of Land use types (LUTs) in Ogun River watershed (ORW) was investigated. ORW was stratified using proportionate sampling technique into Guinea Savannah (GS), Rainforest (RF) and Swamp Forest (SF) Ecological Zones (EZs). Three LUTs: Natural Forest (NF), Disturbed Forest (DF) and Farmland (FL) were purposively selected in GS: GSNF, GSDF, GSFL; RF: RFNF, RFDF, RFFL and SF: SFNF, SFDF, SFFL, respectively. Systematic line transects was used in the laying of the sample plots. Sample plots of 25 m×25 m were established in alternate positions. Ten 1 m×1 m quadrats were randomly laid for soil core sampling from previously randomly selected ten plots. The core samples (10) were pooled per plot in each LUT and placed in individual trays. Ten trays with sterilized soil were used as control. The trays were watered regularly and checked for seedlings emergence fortnightly for 18 months. The experimental design used was 3×3 factorial experiments. ANOVA, Diversity index (H') and Similarity index (SI) were used to analyze the data. There was significant difference in seedling emergence among ecological zones and land use types (p<0.05). A total of 4,400 seedlings emerged from the soil samples. All species were distributed among 32 families. FL in the RF had the highest number of germinated seeds (705±37.33 seedlings) followed by DF in the RF (701±49.6 seedlings). The lowest emergence was in NF of the SF (199±28.41 seedlings). DF in the RF had highest number of species (34) distributed among 22 families. Emergence from soil seed bank of NF in ORW was generally with more of tree species than herbs that were predominant in FL and DF.

A Small-area Hardware Implementation of EGML-based Moving Object Detection Processor (EGML 기반 이동객체 검출 프로세서의 저면적 하드웨어 구현)

  • Sung, Mi-ji;Shin, Kyung-wook
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.21 no.12
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    • pp.2213-2220
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    • 2017
  • This paper proposes an efficient approach for hardware implementation of moving object detection (MOD) processor using effective Gaussian mixture learning (EGML)-based background subtraction method. Arithmetic units used in background generation were implemented using LUT-based approximation to reduce hardware complexity. Hardware resources used for both background subtraction and Gaussian probability density calculation were shared. The MOD processor was verified by FPGA-in-the-loop simulation using MATLAB/Simulink. The MOD performance was evaluated by using six types of video defined in IEEE CDW-2014 dataset, which resulted the average of recall value of 0.7700, the average of precision value of 0.7170, and the average of F-measure value of 0.7293. The MOD processor was implemented with 882 slices and block RAM of $146{\times}36kbits$ on Virtex5 FPGA, resulting in 60% hardware reduction compared to conventional design based on EGML. It was estimated that the MOD processor could operate with 75 MHz clock, resulting in real-time processing of $800{\times}600$ video with a frame rate of 39 fps.