• Journal of Welding and Joining
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• v.34 no.5
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• pp.13-18
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• 2016

Toshiba has developed a laser peening system for PWRs(pressurized water reactors) as well after the one for BWRs(boiling water reactors), and applied it for BMI(bottom-mounted instrumentation) nozzles, core deluge line nozzles and primary water inlet nozzles of Ikata Unit 1 and 2 of Shikoku Electric Power Company since 2004, which are Japanese operating PWR power plants. Laser pulses were delivered through twin optical fibers and irradiated on two portions in parallel to reduce operation time. For BMI nozzles, we developed a tiny irradiation head for small tubes and we peened the inner surface around J-groove welds after laser ultrasonic testing (LUT) as the remote inspection, and we peened the outer surface and the weld for Ikata Unit 2 supplementary. For core deluge line nozzles and primary water inlet nozzles, we peened the inner surface of the dissimilar metal welding, which is of nickel base alloy, joining a safe end and a low alloy metal nozzle. In this paper, the development and the actual application of the laser peening system for PWR power plants will be described.

• Journal of IKEEE
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• v.23 no.4
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• pp.1400-1407
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• 2019

In this paper, we propose a support vector machine (SVM) based gas classifier that can support real-time self-learning. The modified sequential minimal optimization (MSMO) algorithm is employed to train the proposed SVM. By using a shared structure for learning and classification, the proposed SVM reduced the hardware area by 35% compared to the existing architecture. Our system was implemented with 3,337 CLB (configurable logic block) LUTs (look-up table) with Xilinx Zynq UltraScale+ FPGA (field programmable gate array) and verified that it can operate at the clock frequency of 108MHz.

• Journal of Advanced Navigation Technology
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• v.13 no.6
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• pp.846-853
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• 2009

This paper presents the design of a high efficiency frequency multiplier with load-pull simulation and analyses the nonlinear distortion of the frequency multiplier. The frequency multiplier shows serious distortion of multiplying signal bandwidth because of nonlinearity when modulated signal is applied, so a digital predistortion with look up table (LUT) is applied to compensate for the distortion of the frequency multiplier. The frequency multiplier is designed to produce 5.8GHz output by doubling the input frequency to be operating at IEEE 802.11a standard wireless LAN. The output spectrum shows 12dB ACPR improvement both at +11MHz, +20MHz offset from center frequency after linearization.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.263-266
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• 2012

This paper describes an efficient hardware implementation of Whirlpool hash function as ISO/IEC 10118-3 standard. Optimized timing is achieved by using pipelined small LUTs, and Whirlpool block cipher and key schedule have been implemented in parallel for improving throughput. In key schedule, key addition is area-optimized by using inverters and muxes instead of using rom and xor gates. This hardware has been implemented on Virtex5-XC5VSX50T FPGA device. Its maximum operating frequency is about 151MHz, and throughput is about 950Mbps.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.9
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• pp.2388-2404
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• 2012

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

• The Journal of the Korea Contents Association
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• v.13 no.4
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• pp.44-52
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• 2013

The SIFT algorithm is being actively researched for various image processing applications including video surveillance and autonomous vehicle navigation. The computation of sin/cos function is the most cost part needed in whole computational complexity and time for SIFT descriptor. In this paper, we implement a hardware to sin/cos function of descriptor on sift feature detection algorithm. The proposed Sin/Cosine processor is coded in Verilog and synthesized and simulated using Xilinx ISE 9.2i. The processor is mapped onto the device Spartan 2E (XC2S200E-PQ208-6). It consumes 149 slices, 233 LUTs and attains a maximum operation frequency of 60.01 MHz. As compared with the software realization, our FPGA circuit can achieve the speed improvement by 40 times in average.

• Journal of Institute of Control, Robotics and Systems
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• v.3 no.6
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• pp.626-631
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• 1997

This paper represents the design of a real-time image preprocessing system. The preprocessing system performs hardware-wise mask operations and thresholding operations at the speed of camera output single rate. The preprocessing system consists of the preprocessing board and the main processing board. The preprocessing board includes preprocessing unit that includes a $5\times5$ mask processor and LUT, and can perform mask and threshold operations in real-time. To achieve high-resolution image input data($20485\timesn$), the preprocessing board has a linescan camera interface. The main processing board includes the image processor unit and main processor unit. The image processor unit is equipped with TI's TMS320C32 DSP and can perform image processing algorithms at high speed. The main processor unit controls the operation of total system. The proposed system is faster than the conventional CPU based system.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.5
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• pp.297-305
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• 2015

AFLS (Adaptive front lighting System) is being applied to improve safety in driving automotive at night. Safe embedded system for controlling head-lamp has to be tightly designed by considering safety requirement of hardware-dependent software, which is embedded in automotive ECU(Electronic Control Unit) hardware under severe environmental noise. In this paper, we propose an adaptive headlight controller with newly-designed symmetric angle sensor compensator, which is integrated with ECU-based adaptive front light system. The proposed system, on which additional backup hardware and emergency control algorithm are integrated, effectively detects abnormal situation and restore safe status of controlling the light-angle in AFLS operations by comparing result in symmetric angle sensor. The controlled angle value is traced into internal memory in runtime and will be continuously compared with the pre-defined lookup table (LUT) with symmetric angle value, which is used in normal operation. The watch-dog concept, which is based on using angle sensor and control-value tracer, enables quick response to restore safe light-controlling state by performing the backup sequence in emergency situation.

• Proceedings of the KSRS Conference
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• 2003.11a
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• pp.1255-1257
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• 2003

This study proposes a single-channel satellite remote sensing algorithm for retrieving aerosol optical thickness over global ocean using FY-1C/1D data. An efficient lookup table (LUT)method is adopted in this algorithm to generate apparent reflectance in channel 1 and channel 2 of FY-1C/1D over ocean. The algorithm scale the apparent reflectance in cloud-free conditions to aerosol optical thickness using a state-of-art radiative transfer model 6S with input of the relative spectral response of channel 1 and 2 of FY-1C/1D. Monthly mean composite maps of the aerosol optical thickness have been obtained from FY-1C/1D global area coverage data between 2001 and 2003. Aerosol optical thickness maps can show the major aerosol source which are located off the west coast of northern and southern Africa, Arabian Sea and India Ocean. These result is very similar to other satellite sensors such as AVHRR and MODIS in the location area of heavy aerosol optical thickness over global ocean. The algorithm have been used to FY-1D operational performance and it is the first operational aerosol remote sensing product in China.

• Korean Journal of Remote Sensing
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• v.32 no.1
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• pp.67-71
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• 2016

The surface reflectance is essential to retrieval various indicators related land properties such as vegetation index, albedo and etc. In this study, we estimated surface reflectance using Himawari-8 / Advanced Himawari Imager (AHI) channel data. In order to estimate surface reflectance from Top of Atmosphere (TOA) reflectance, the atmospheric correction is necessary because all of the TOA reflectance from optical sensor is affected by gas molecules and aerosol in the atmosphere. We used Second Simulation of a Satellite Signal in the Solar Spectrum Vector (6SV) Radiative Transfer Model (RTM) to correct atmospheric effect, and Look-Up Table (LUT) to shorten the calculation time. We verified through comparison Himawri-8 / AHI surface reflectance and Proba-V S1 products. As a result, bias and Root Mean Square Error (RMSE) are calculated about -0.02 and 0.05.