• Proceedings of the Korea Information Processing Society Conference
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• 2015.10a
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• pp.396-397
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• 2015

본 논문에서는 이동 물체의 연속 위치 추적을 위한 무선 저전력 기저대역 모뎀을 설계 및 구현하였다. 설계된 모뎀은 단일 하드웨어로 16칩 및 32칩 대역확산을 통해 900MHz 대역 및 2.4GHz 대역을 동시에 지원하며, 250Kbps 이하 가변전송률 전송을 통해 다양한 통달거리 지원이 가능하다. FPGA 기반 구현 결과, 설계된 기저대역 모뎀은 8,010 Slice, 20,672 Slice LUT, 25,512 Flip Flop, 18Kb Block RAM으로 구성되었음을 확인하였다.

• Korean Journal of Remote Sensing
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• v.23 no.3
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• pp.171-179
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• 2007

Hyperspectral images have shown a great potential for the applications in resource management, agriculture, mineral exploration and environmental monitoring. However, due to the large volume of data, processing of hyperspectral images faces some difficulties. This paper introduces the development of an image processing tool (HYVIEW) that is particularly designed for handling hyperspectral image data. Current version of HYVIEW is dealing with efficient algorithms for displaying hyperspectral images, selecting bands to create color composites, and atmospheric correction. Three band-selection schemes for producing color composites are available based on three most popular indexes of OIF, SI and CI. HYVIEW can effectively demonstrate the differences in the results of the three schemes. For the atmospheric correction, HYVIEW utilizes a pre-calculated LUT by which the complex process of correcting atmospheric effects can be performed fast and efficiently.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2018.06a
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• pp.182-184
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• 2018

본 논문에서는 HDR 영상 신호의 고속 광전변환을 위한 파라미터 룩업 테이블 기반 구간 선형 근사 방법을 제안한다. 제안하는 방법은 고속화하기 위한 광전변환함수의 입력 값의 범위를 다수개의 구간으로 나누고 각 구간마다 별도의 선형 근사함수를 구하여 광전변환함수를 근사하고 각 구간별로 필요한 선형 근사함수의 파라미터를 룩업 테이블에 미리 저장하고 사용함으로써 보다 빠른 근사 값 계산이 가능하다. 제안한 방법의 성능 평가를 위해 MPEG 에서 제공하는 참조 소프트웨어인 HDRTools 를 기반으로 실험을 수행했고 이를 통해 참조 소프트웨어에 구현되어 있는 기존의 고속화 방법과 비교하여 더 적은 연산 수를 가지며 평균 24% 빠른 처리속도와 약 0.05dB 의 평균 PSNR 손실을 보임을 확인하였다.

• The Transactions of the Korean Institute of Power Electronics
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• v.27 no.2
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• pp.118-125
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• 2022

With the aim to maximize the use of a given voltage source in the field of railway and electric vehicles, this study applies a technique for controlling the overmodulation region between the linear and the six-step regions. High linearity overmodulation techniques that do not use look-up table (LUT) to digital signal processor (DSP) using carrier based pulse width modulation (PWM) are proposed. Such technique requires the phase of the voltage vector at the point where the circular trajectory of the voltage command vector and hexagonal cross each other. Therefore, a method is proposed to obtain a phase of a voltage vector that is derived through an equation and applied to a carrier-based PWM. Validity of the proposed implementation method is confirmed through simulation and experiment.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.3
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• pp.126-133
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• 2003

This paper is related to a morphological segmentation method for extracting the moving object in video sequence using global motion compensation and two-dimensional spatio-temporal entropic thresholding. First, global motion compensation is performed with camera panning vector estimated in the hierarchical pyramid structure constructed by wavelet transform. Secondly, the regions with high possibility to include the moving object between two consecutive frames are extracted block by block from the global motion compensated image using two-dimensional spatio-temporal entropic thresholding. Afterwards, the LUT classifying each block into one among changed block, uncertain block, stationary block according to the results classified by two-dimensional spatio-temporal entropic thresholding is made out. Next, by adaptively selecting the initial search layer and the search range referring to the LUT, the proposed HBMA can effectively carry out fast motion estimation and extract object-included region in the hierarchical pyramid structure. Finally, after we define the thresholded gradient image in the object-included region, and apply the morphological segmentation method to the object-included region pixel by pixel and extract the moving object included in video sequence. As shown in the results of computer simulation, the proposed method provides relatively good segmentation results for moving object and specially comes up with reasonable segmentation results in the edge areas with lower contrast.

• The Journal of the Korea Contents Association
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• v.10 no.6
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• pp.329-335
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• 2010

Digital imaging detectors can use a variety of detection materials to convert X-ray radiation either to light or directly to electron charge. Many detectors such as amorphous silicon flat panels, CCDs, and CMOS photodiode arrays incorporate a scintillator screen to convert x-ray to light. The digital radiography systems based on semiconductor detectors, commonly referred to as flat panel detectors, are gaining popularity in the clinical & hospital. The X-ray detectors are described between a-Silicon based indirect type and a-Selenium based direct type. The DRS of detectors is used to convert the x-ray to electron hole pairs. Image processing is described by specific image features: Latitude compression, Contrast enhancement, Edge enhancement, Look up table, Noise suppression. The image features are tuned independently. The final enhancement result is a combination of all image features. The parameters are altered by using specific image features in the different several hospitals. The image in a radiological report consists of two image evaluation processes: Clinical image parameters and MTF is a descriptor of the spatial resolution of a digital imaging system. We used the edge test phantom and exposure procedure described in the IEC 61267 to obtain an edge spread function from which the MTF is calculated. We can compare image in the processing parameters to change between original and processed image data. The angle of the edge with respect to the axes of detector was varied in order to determine the MTF as a function of direction. Each MTF is integrated within the spatial resolution interval of 1.35-11.70 cycles/mm at the 50% MTF point. Each image enhancement parameters consists of edge, frequency, contrast, LUT, noise, sensitometry curve, threshold level, windows. The digital device is also shown to have good uniformity of MTF and image parameters across its modality. The measurements reported here represent a comprehensive evaluation of digital radiography system designed for use in the DRS. The results indicate that the parameter enables very good image quality in the digital radiography. Of course, the quality of image from a parameter is determined by other digital devices in addition to the proper clinical image.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.7
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• pp.29-38
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• 2009

In this paper, a high performance pipelined computing design of parallel multiplier-temporal buffer-parallel accumulator is present for the convolution-based non-cascaded architecture aiming at the real time Discrete Wavelet Transform(DWT) processing. The convolved multiplication of DWT would be reduced upto 1/4 by utilizing the filter coefficients symmetry and the up/down sampling; and it could be dealt with 3-5 times faster computation by LUT-based DA multiplication of multiple filter coefficients parallelized for product terms with an image data. Further, the reutilization of computed product terms could be achieved by storing in the temporal buffer, which yields the saving of computation as well as dynamic power by 50%. The convolved product terms of image data and filter coefficients are realigned and stored in the temporal buffer for the accumulated addition. Then, the buffer management of parallel aligned storage is carried out for the high speed sequential retrieval of parallel accumulations. The convolved computation is pipelined with parallel multiplier-temporal buffer-parallel accumulation in which the parallelization of temporal buffer and accumulator is optimize, with respect to the performance of parallel DA multiplier, to improve the pipelining performance. The proposed architecture is back-end designed with 0.18um library, which verifies the 30fps throughput of SVGA(800$\times$600) images at 90MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.12
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• pp.1339-1349
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• 2008

In this paper, a nonlinear relationship between an input complex envelope and an output complex envelope of m-th harmonic zone is theoretically analyzed, and AM/$AM_m$ and AM/$PM_m$ are defined. A scheme to extract these characteristics from measured in-phase and quadrature-phase data is suggested. The proposed analysis is verified with a fundamental-fundamental and fundamental-third harmonic measurements for a InGaP power amplifier(PA). Based on the harmonic-band nonlinear analysis and extraction scheme, a new technique to send a signal in m-th harmonic band with a harmonic signal Linearization Digital Predistortion(DPD) scheme is presented. A numerical analysis and a Look-Up Table(LUT) based DPD algorithms to linearize output signal on m-th harmonic zone are developed. For a 16- and a 64-QAM input signals, a DPD for third harmonic signal linearization is implemented, and output spectrum and signal constellation are measured. The wholly distorted signals are linearized, and thus the measured Error Vector Magnitudes (EVM) are 6.4 % and 6.5 % respectively. The results show that a proposed scheme linearizes a nonlinearly distorted harmonic band signals. The proposed nonlinear analysis and predistortion scheme can be applied to multiband transmitter in next generation software defined radio(SDR)/cognitive radio(CR) wireless system.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.7 s.361
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• pp.71-80
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• 2007

This paper describes an efficient hardware design of WiBro security processor (WBSec) supporting for the security sub-layer of WiBro wireless internet system. The WBSec processor, which is based on AES (Advanced Encryption Standard) block cipher algorithm, performs data oncryption/decryption, authentication/integrity, and key encryption/decryption for packet data protection of wireless network. It carries out the modes of ECB, CTR, CBC, CCM and key wrap/unwrap with two AES cores working in parallel. In order to achieve an area-efficient implementation, two design techniques are considered; First, round transformation block within AES core is designed using a shared structure for encryption/decryption. Secondly, SubByte/InvSubByte blocks that require the largest hardware in AES core are implemented using field transformation technique. It results that the gate count of WBSec is reduced by about 25% compared with conventional LUT (Look-Up Table)-based design. The WBSec processor designed in Verilog-HDL has about 22,350 gates, and the estimated throughput is about 16-Mbps at key wrap mode and maximum 213-Mbps at CCM mode, thus it can be used for hardware design of WiBro security system.