• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.54-58
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• 2007

Development of high performance LTPS TFTs contributed to open up new SOP technology with various digital circuits integrated in display panels. This work introduces the current mode logic(CML) gate design method with which one can replace slow CMOS logic gates. The CML inverter exhibited small logic swing, fast response with high power consumption. But the power consumption became compatible with CMOS gates at higher clock speed. Due to small current values in CML, layout area is smaller than the CMOS counterpart even though CML uses larger number of devices. CML exhibited higher noise immunity thanks to its non-inverting and inverting outputs. Multi-input NAND/AND and NOR/OR gates were implemented by the same circuit architecture with different input confirugation. Same holds for MUX and XNOR/XOR CML gates. We concluded that the CML gates can be designed with few simple circuits and they can improve power consumption, chip area, and speed of operation.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.900-904
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• 2011

In this paper, we investigated an anomalous hump phenomenon under the positive bias stress in p-type LTPS TFTs. The devices with inferior electrical performance also show larger hump phenomenon. which can be explained by the sub-channel induced from trapped electrons under thinner gate oxide region. We can confirm that the devices with larger hump have larger interface trap density ($D_{it}$) and grain boundary trap density ($N_{trap}$) extracted by low-high frequency capacitance method and Levinson-Proano method, respectively. From the C-V with I-V transfer characteristics, the trapped electrons causing hump seem to be generated particularly from the S/D and gate overlapped region. Based on these analysis, the major cause of an anomalous hump phenomenon under the positive bias stress in p-type poly-Si TFTs is explained by the GIDL occurring in the S/D and gate overlapped region and the traps existing in the channel edge region where the gate oxide becomes thinner, which can be inferred by the fact that the magnitude of the hump is dependent on the average trap densities.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.447-447
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• 2013

최근 전자산업의 발전으로 차세대 디스플레이 소자로 산화물반도체가 주목받고 있다. 산화물 반도체는 저온공정, 높은 이동도 및 투과율을 가지기 때문에 이러한 공정이나 물성 측면에 있어 기존의 a-Si, LTPS 등을 대채할 만한 소자로서 연구가 활발이 이루어지고 있다. 특히 고해상도 및 고속구동이 진행됨에 따라 높은 이동도의 필요성이 대두되고 있다. 본 연구에서는 IGZO 산화물 반도체 박막트랜지스터의 이동도 개선을 위해 나노입자를 사용하였다. 게이트전극으로 사용된 Heaviliy doped P-type Si 기판위에 200 nm의 SiO2 절연층을 성장시킨 후, 채널로 작동하기 위한 IGZO 박막을 증착하기 전에 10~20 nm 크기의 니켈, 금 나노입자를 부착시켰다. 열처리 온도는 $350^{\circ}C$, 90분동안 진행하였고, 100 nm의 알루미늄 전극을 증착시켜 TFT 소자를 제작하였다. TFT 소자가 동작할 시, IGZO 박막 내부의 전자들은 게이트 전압으로 인해 하부로 이동하여 채널을 형성, 동시에 드레인 전압으로 인한 캐리어들의 움직임으로 인해 소자가 동작하게 된다. 본 연구에서는 채널이 형성되는 계면 부근에 전도성이 높은 금속 나노입자를 부착시켜 다수 캐리어인 전자가 채널을 통과할 때 전류흐름에 금속 나노입자들이 기여하여 전기적 특성의 변화에 어떠한 영향을 주는지 연구하였다. 반응시간을 조절하여 기판에 붙는 나노입자의 밀도 변화에 따른 특성과 다양한 크기(5, 10, 20 nm)를 갖는 금, 니켈 나노입자를 포함한 IGZO TFTs 소자를 제작하여 전달특성, 출력특성의 변화를 비교하였고, 실질적인 채널길이의 감소효율과 캐리어 이동도의 변화를 비교분석 하였다.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.3
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• pp.279-284
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• 2014

This paper proposes a novel OLED pixel circuit to compensate the threshold voltage variation of p-channel low temperature polycrystalline silicon thin-film transistors (LTPS TFTs). The proposed 5-TFT OLED pixel circuit consists of 4 switching TFTs, 1 OLED driving TFT and 1 capacitor. One frame of the proposed pixel circuit is divided into initialization period, threshold voltage sensing and data programming period, data holding period and emission period. SmartSpice simulation results show that the maximum error rate of OLED current is -4.06% when the threshold voltage of driving TFT varies by ${\pm}0.25V$ and that of OLED current is 9.74% when the threshold voltage of driving TFT varies by ${\pm}0.50V$. Thus, the proposed 5T1C pixel circuit can realize uniform OLED current with high immunity to the threshold voltage variation of p-channel poly-Si TFT.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.2
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• pp.207-212
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• 2013

A novel pixel circuit that uses only n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (LTPS-TFTs) to compensate the threshold voltage variation of a OLED driving TFT is proposed. The proposed 6T1C pixel circuit consists of 5 switching TFTs, 1 OLED driving TFT and 1 capacitor. When the threshold voltage of driving TFT varies by ${\pm}0.33$ V, Smartspice simulation results show that the maximum error rate of OLED current is 7.05 % and the error rate of anode voltage of OLED is 0.07 % at Vdata = 5.75 V. Thus, the proposed 6T1C pixel circuit can realize uniform output current with high immunity to the threshold voltage variation of poly-Si TFT.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.1258-1261
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• 2004

Degradation phenomenon in the low-temperature polysilicon (LTPS) thin-film transistors (TFTs) with different junction structures was investigated. A gate-overlapped lightly doped drain (GOLDD) structure showed better hot-carrier stress (HCS) stability than a conventional LDD one. On the other hand, high drain current stress (HDCS) at $V_{gs}$ = $V_{ds}$ conditions caused much severe device degradation in the GOLDD structure because of its higher current level resulting in the higher applied power. It is suggested that self-heating-induced mobility degradation in the GOLDD TFFs be suppressed for using this structure in short-channel devices.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.10a
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• pp.43.1-43.1
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• 2011

Hydrogenated amorphous Si (a-Si:H), low temperature poly Si (LTPS) 등 기존 thin film transistors (TFTs)에 사용되던 채널 물질을 대체할 재료로써 다양한 연구가 진행되고 있는 amorphous indium-gallium-zinc-oxide (a-IGZO)는 TFT에 적용하였을 때 뛰어난 전기적 특성과 재연성을 나타낼 뿐만 아니라 넓은 밴드갭을 가져 투명소자로도 응용이 가능하다. 본 연구에서는 a-IGZO의 열처리에 따른 소자의 전기적 특성과 조성 분포의 관계를 확인하기 위해 다음과 같이 실험을 진행하였다. Si/SiO2 기판 위에 DC sputter를 이용하여 IGZO를 증착하고 $350^{\circ}C$에서 열처리를 한 후 evaporator로 Al 전극을 형성시켰다. 이 때 전기적 특성의 변화를 비교하기 위해 열처리 한 샘플과 열처리 하지 않은 샘플에 대해 I-V 특성을 측정하였고, 채널 내부의 조성 분포 변화를 transmission electron microscopy (TEM)의 energy dispersive spectrometer (EDS)를 이용하여 관찰하였다. 그 결과 열처리 된 a-IGZO 채널 층의 산소 비율이 감소하였으며 전체적인 조성이 고르게 분포 되었고 전기적 특성은 향상되었다.

• Journal of Information Display
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• v.11 no.1
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• pp.12-16
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• 2010

The effect of the crystallization and activated annealing of Si films using an excimer laser and the new CW blue laser are described and compared with furnace annealing for application in advanced TFTs and for future applications. Pulsed excimer laser annealing (ELA) is currently being used extensively as a low-temperature poly-silicon (LTPS) process on glass substrates as its efficiency is high in the ultra-violet (UV) region for thin Si films with thickness of 40-60 nm. ELA enables extremely low resistivity relating to high crystallinity for both the n- and p-type Si films. On the other hand, CW blue laser diode annealing (BLDA) enables the smooth Si surface to have arbitral crystal grains from micro-grains to an anisotropic huge grain structure only by controlling its power density. Both annealing techniques are expected to be applied in the future advanced TFT systems.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.399-402
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• 2006

A new voltage-scaled compensation pixel which employs 3 p-type poly-Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the $V_{TH}$ memorizing and cancellation, but scales down the inevitable $V_{TH}$ variation of poly-Si TFT. Also the troublesome narrow input range of $V_{DATA}$ is increased and the $V_{DD}$ supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.1283-1286
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• 2006

A holding latch with level shifting function is proposed for power and cost effectiveness with low temperature polycrystalline silicon technology on the glass backplane. Layout area and power consumption of the proposed circuit are reduced by 10% and 52% compared with those of the typical structure which combines a static D-latch and a cross coupled level shifter for 2.2" qVGA panel, respectively.