• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.3
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• pp.303-310
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• 2013

Underwater acoustic communication has multipath error because of reflection by sea-level and sea-bottom. The multipath of underwater channel causes signal distortion and error floor. In order to improve the performance, it is necessary to employ an iterative coding scheme. Among the iterative coding scheme, turbo codes and LDPC codes are dominant channel coding schemes in recent. This paper concluded that turbo coding scheme is optimal for underwater communications system in aspect to performance, coded word length, and equalizer combining. Also, we confirmed the performance in the environment of oceanic experimentation using turbo equalizer based on distance 5Km, data rate 1Kbps.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.399-401
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• 2013

In this paper, we present the method to impove the performance by using iterative decoding in LDPC codes with 8-PSK modulation. Iterative decoding is the technique that improve the performance after the input signals of receiver are re-calculated by using the soft decision output of decoder. DVB-S2 system with 8-PSK modulation based on iterative decoding had a better performance than DVB-S2 with 8-PSK modulation over Gaussian channels.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2006.07a
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• pp.490-490
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• 2006

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.10 no.12
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• pp.5401-5421
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• 2016

Both low-density parity-check (LDPC) codes and the multiple access technique of spatially coupling data transmission (SCDT) can be expressed in bipartite graphs. To improve the performance of iterative demodulation and decoding for SCDT, a novel joint sparse graph (JSG) with SCDT and LDPC codes is constructed. Based on the JSG, an approach for iterative joint demodulation and decoding by belief propagation (BP) is presented as an exploration of the flooding schedule, and based on BP, density evolution equations are derived to analyze the performance of the iterative receiver. To accelerate the convergence speed and reduce the complexity of joint demodulation and decoding, a novel serial schedule is proposed. Numerical results show that the joint demodulation and decoding for SCDT based on JSG can significantly improve the system's performance, while roughly half of the iterations can be saved by using the proposed serial schedule.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.423-426
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• 2005

In this paper, we propose a receiver that combines a channel detector with a channel decoder to retrieve information from ISI and AWGN in an iteratively manner. The receiver, evolving from a system of a PRML detector and a RS decoder, consists of a SOVA detector followed by a LDPC decoder and has them exchange information iteratively. Rather than handling extrinsic reliabilities explicitly as in Turbo equalization, we take hard-decision values from the LDPC decoder and mix them with the channel output in a certain ratio as input for SOVA. The scheme, simply modified to the one-way structure of a SOVA and a LDPC decoder, shows improved performance with iteration numbers as well as the combining ratio of the channel output and the feedback output. We additionally analyze the receiver with a simple theoretical model and present some valuable properties.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.1-5
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• 2008

Although we can make a sparse matrices for LDPC codes, the encoding complexity per a block increases quadratically by $n^2$. We propose modified PEG algorithm using PEG algorithm having a large girth by establishing edges or connections between symbol and check nodes in an edge-by-edge manner. M-PEG construct parity check matrices. So we propose parity check matrices H form a dual-diagonal matrices that can construct a more efficient decoder using a M-PEG(modified Progressive Edge Growth).

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.1
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• pp.8-14
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• 2013

A low density parity check (LDPC) decoder provides a most powerful error control capability for mobile communication devices and storage systems, due to its performance being close to Shannon's limit. In this paper, we introduce an efficient overlapped LDPC decoding algorithm using a upper dual-diagonal parity check matrix structure. By means of this algorithm, the LDPC decoder can concurrently execute parts of the check node update and variable node update in the sum-product algorithm. In this way, we can reduce the number of clock cycles per iteration as well as reduce the total latency. The proposed decoding structure offers a very simple control and is very flexible in terms of the variable bit length and variable code rate. The experiment results show that the proposed decoder can complete the decoding of codewords within 70% of the number of clock cycles required for a conventional non-overlapped decoder. The proposed design also reduces the power consumption by 33% when compared to the non-overlapped design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.3A
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• pp.151-156
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• 2012

In this paper, design of quasi-cyclic(QC) low-density parity-check codes is proposed to have full diversity for space-time bit-interleaved coded modulation(ST-BICM) systems. Necessary and sufficient conditions that the proposed scheme has full diversity are proved as the condition that submatrices corresponding to the system part of codewords are invertible. And new construction method of binary invertible matrices for QC LDPC codes in ST-BICM systems are also proposed and modification for parity-check matrices are also explained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.4
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• pp.419-426
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• 2014

This paper proposes a high-throughput encoding process and encoder architecture for quasi-cyclic low-density parity-check codes in IEEE 802.11ac standard. In order to achieve the high throughput with low complexity, a partially parallel processing based encoding process and encoder architecture are proposed. Forward and backward accumulations are performed in one clock cycle to increase the encoding throughput. A low complexity cyclic shifter is also proposed to minimize the hardware overhead of combinational logic in the encoder architecture. In IEEE 802.11ac systems, the proposed encoder is rate compatible to support various code rates and codeword block lengths. The proposed encoder is implemented with 130-nm CMOS technology. For (1944, 1620) irregular code, 7.7 Gbps throughput is achieved at 100 MHz clock frequency. The gate count of the proposed encoder core is about 96 K.

• ETRI Journal
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• v.31 no.5
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• pp.585-592
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• 2009

This paper presents a method for decoding high minimal distance ($d_{min}$) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher$d_{min}$ than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high $d_{min}$, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof-of-concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25-${\mu}m$ CMOS. It outperforms an equivalent LDPC-like decoder by 1 dB at BER=$10^{-5}$ and is 44 percent smaller and consumes 28 percent less energy per decoded bit.