• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.371-378
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• 2015

In this paper, a different type of pulse width modulation (PWM) control scheme for a buck converter is introduced. The proposed buck converter uses PWM with frequency hopping and a low quiescent.current low dropout (LDO) voltage regulator with a power supply rejection ratio enhancer to reduce high spurs, harmonics and output voltage ripples. The low quiescent.current LDO voltage regulator is not described in this paper. A three-bit binary-to-thermometer decoder scheme and voltage ripple controller (VRC) is implemented to achieve low voltage ripple less than 3mV to increase the efficiency of the buck converter. An internal clock that is synchronized to the internal switching frequency is used to set the hopping rate. A center frequency of 2.5MHz was chosen because of the bluetooth low energy (BLE) application. This proposed DC-DC buck converter is available for low-current noise-sensitive loads such as BLE and radio frequency loads in portable communications devices. Thus, a high-efficiency and low-voltage ripple is required. This results in a less than 2% drop in the regulator's efficiency, and a less than 3mV voltage ripple, with -26 dBm peak spur reduction operating in the buck converter.

• ETRI Journal
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• v.39 no.3
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• pp.373-382
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• 2017

A new internally compensated low drop-out voltage regulator based on the cascoded flipped voltage follower is presented in this paper. Adaptive biasing current and fast charging/discharging paths have been added to rapidly charge and discharge the parasitic capacitance of the pass transistor gate, thus improving the transient response. The proposed regulator was designed with standard 65-nm CMOS technology. Measurements show load and line regulations of $433.80{\mu}V/mA$ and 5.61 mV/V, respectively. Furthermore, the output voltage spikes are kept under 76 mV for 0.1 mA to 100 mA load variations and 0.9 V to 1.2 V line variations with rise and fall times of $1{\mu}s$. The total current consumption is $17.88{\mu}V/mA$ (for a 0.9 V supply voltage).

• Information and Communications Magazine
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• v.30 no.11
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• pp.60-67
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• 2013

본 원고에서는 무선 전력 전송용 송수신 칩의 구조 및 설계 이슈에 대해서 설명하고, 각 구성 블록들의 동작 원리를 살펴본다. 또한, 무선 전력 전송의 효율을 향상시키기 위한 시스템 구조 및 Rectifier, DC-DC Converter, LDO Regulator, Power Amp 등에 대해서 기본적인 동작 원리부터 최근 설계 동향에 대해서 다룬다.

• Journal of IKEEE
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• v.14 no.2
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• pp.90-97
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• 2010

The high efficiency power management IC(PMIC) with DTMOS(Dynamic Threshold voltage MOSFET) switching device and DTMOS Error Amplifier is presented in this paper. PMIC is controlled with PWM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS(DT-CMOS) with low on-resistance is designed to decrease conduction loss. The control parts in Buck converter, that is, PWM control circuits consist of a saw-tooth generator, a band-gap reference circuit, an DT-CMOS error amplifier and a comparator circuit as a block. the proposed DT-CMOS Error Amplifier has 72dB DC gain and 83.5deg phase margin. also Error Amplifier that use DTMOS more than CMOS showed power consumption decrease of about 30%. DC-DC converter, based on Voltage-mode PWM control circuits and low on-resistance switching device is achieved the high efficiency near 96% at 100mA output current. And DC-DC converter is designed with Low Drop Out regulator(LDO regulator) in stand-by mode which fewer than 1mA for high efficiency.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.2
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• pp.85-90
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• 2009

This paper presents a single supply PLC SoC ASIC with a built-in analog Front-end circuit. To achieve the low power consumption along with low cost, this PLC SoC employs fully CMOS Analog Front End (AFE) and several LDO regulators (LDOs) to provide the internal power for Logic Core, DAC and Input/output Pad driver. The receiver part of the AFE consists of Pre-amplifier, Gain Amplifier and 1 bit Comparator. The transmitter part of the AFE consists of 10 bit Digital Analog Converter and Line Driver. This SoC is implemented with 0.18 ${\mu}m$ 1 Poly 5 Metal CMOS Process. The single supply voltage is 3.3 V and the internal powers are provided using LDOs. The total power consumption is below 30 mA at stand-by mode to meet the Eco-Design requirement. The die size is 3.2 $\times$ 2.8 $mm^{2}$.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.6
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• pp.135-140
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• 2021

In this paper is a study on system design to prevent accidents using accelerometers. A switching power FET was configured at the power supply stage, and DC-DC converter, a regulator, and an LDO were designed for the power supply. In order to solve the power problem at once, it was divided into two parts, and a 3-axis accelerometer was designed to extract motion information to safely prevent accidents. Microprocessor enables communication through I2C and UART communication ports, and enables debugging through J-LINK. As a result of measuring the acceleration sensor data, it was confirmed that the power is normally cut off to prevent accidents when motion at an angle of 30° or more is detected.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.120-128
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• 2017

This paper describes a neural stimulation system that employs an inductive coupling link to transfer power and data wirelessly. For the reliable data and power delivery, a self-referenced amplitude-shift keying (ASK) demodulator and a wide-range voltage regulator are suggested and implemented in the proposed stimulator system. The prototype fabricated in 0.35 um BCD process successfully transferred 1.2 Kbps data bi-directionally while supplying 4.5 mW power to internal MCU and stimulation block.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.5
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• pp.893-899
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• 2008

Behavioral level simulations of LDO voltage regulator and phase locked loop(PLL) are performed with CPPSIM, a behavioral-level simulation tool based on C language. The validity of the simulation tool is examined by modeling analog circuits and simulating the circuits. In addition, the designed PLL adopted digital architecture to possess advantages of digital circuits.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.7
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• pp.571-575
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• 2017

This paper presents a C-band bi-directional T/R chipset in $0.13{\mu}m$ TSMC CMOS technology for phased array antenna. The T/R chipset, which is a key component of phased array antenna, consists of a 6 bit phase shifter, a 6 bit step attenuator, and three bi-directional gain amplifiers. The phase shifter is controlled up to $354^{\circ}$ with $5.625^{\circ}$ phase step for precise beam steering. The step attenuator is also controlled up to 31.5 dB with 0.5 dB attenuation step for the side lobe level rejection. The LDO(Low Drop Output) regulator for stable 1.2 V DC power and the SPI(Serial Peripheral Interface) for digital control are integrated in the chipset. The chip size is $2.5{\times}1.5mm^2$ including pads.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.4
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• pp.26-33
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• 2010

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and $I^2C$ for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 $mm^2$.