• Title/Summary/Keyword: LDD/Offset structured poly-Si TFT`s

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Electrical Characteristics of Poly-Si TFT`s with Improved Degradation (열화가 억제된 다결정 실리콘 박막 트랜지스터의 전기적 특성)

  • 변문기;이제혁;백희원;김동진;김영호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1999.11a
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    • pp.457-460
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    • 1999
  • The effects of electrical positive stress on n-channel LDD and offset structured poly-Si TFT\`s have been systematically investigated in order to analyze the transfer curve\`s shift mechanism. It has been found that the LDD and offset regions behave as a series resistance that reduce the electric field near drain. Hot carrier effects are reduced because of these results. After electrical stress transfer curve’s shift and variation of the off-current are dependent upon the offset length rather than offset region’s doping concentration. Variation of the subthreshold slope is dependent upon offset region’s doping concentration as well as offset length.

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Analysis on Degradation of Poly-Si TFT`s and Fabrication of Depressed Poly-Si TFT (열화가 억제된 다결성 실리콘 박막 트랜지스터의 제작 및 소자의 열화 특성 분석)

  • Kim, Yong-Sang;Park, Jin-Seok;Jo, Bong-Hui;Gil, Sang-Geun;Kim, Yeong-Ho
    • The Transactions of the Korean Institute of Electrical Engineers C
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    • v.50 no.10
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    • pp.489-493
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    • 2001
  • The on-current of offset and LDD structured devices in slightly decreased while the off-current are remarkably reduced and almost constant independent of gate and drain voltage because offset and LDD regions behave as a series resistance and reduce the lateral electric field in the drain depletion. Degradation of these devices is dependent upon the offset and LDD length rather than doping concentration in these regions. Also, degradation mechanism has been related to the interface generation rather than the hot carrier injection into gate oxide.

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