• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1185-1192
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• 2008

In this paper, a wideband LC oscillator which is composed of a high voltage switch and a fat dipole antenna was designed and radiation characteristics are analyzed. A Marx generator was used as a high voltage pulse generator of the proposed wideband LC oscillator and $90^{\circ}$ corner reflector was used to obtain high directivity. According to simulated and measured results, 3 dB bandwidth of high voltage switch without fat dipole based on the received power is about 9%(${\lambda}_1=0.7\;m$) and bandwidth Is about 30%(${\lambda}_2=1\;m$) by using the LC oscillator containing high voltage switch and fat dipole. Consequently, fat dipole affects not only radiating power but also operating frequency and bandwidth of the LC oscillator. This study will be useful to determine operating frequency and radiating power when we design LC oscillator which uses a high voltage switch and a fat dipole.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.506-510
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• 2016

A triple-band (TB) oscillator was implemented in the TSMC $0.18{\mu}m$ 1P6M CMOS process, and it uses a cross-coupled nMOS pair and two shunt $4^{th}$ order LC resonators to form a $6^{th}$ order resonator with three resonant frequencies. The oscillator uses the varactors for band switching and frequency tuning. The core current and power consumption of the high (middle, low)- band core oscillator are 3.59(3.42, 3.4) mA and 2.4(2.29, 2.28) mW, respectively at the dc drain-source bias of 0.67V. The oscillator can generate differential signals in the frequency range of 8.04-8.68 GHz, 5.82-6.15 GHz, and 3.68-4.08 GHz. The die area of the triple-band oscillator is $0.835{\times}1.103mm^2$.

• Journal of Electrical Engineering and Technology
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• v.13 no.1
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• pp.220-225
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• 2018

A class E power oscillator is demonstrated for 6.78-MHz wireless power transfer system. The oscillator is designed with a class E power amplifier to use an LC feedback network with a high-Q inductor between the input and the output. Multiple capacitors are used to minimize the variation of the oscillation frequency by capacitance tolerance. The gate and drain bias voltages with opposite characteristics to make the frequency shift of the oscillator are connected in a resistance distribution circuit located at the output of the low drop-out regulator and supplied bias voltages for class E operation. The measured output of the class E power oscillator, realized using the co-simulation, shows 9.2 W transmitted power, 6.98 MHz frequency and 86.5% transmission efficiency at the condition with 20 V $V_{DS}$ and 2.4 V $V_{GS}$.

• Journal of IKEEE
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• v.24 no.4
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• pp.975-981
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• 2020

A 10 GHz LC voltage-controlled oscillator (VCO), which controls an amplitude of output signal, is proposed to improve the phase noise. The proposed amplitude control circuit for the LC VCO consists of a peak detector, an amplifier, and a current source. The peak detector is performed detecting the lowest voltage of the output signal by using two diode-connected NMOSFET and a capacitor. The proposed 10 GHz LC VCO with an amplitude control circuit for output signal is designed using a 55 nm CMOS process with a supply voltage of 1.2 V. Its area is 0.0785 ㎟. The amplitude control circuit used in the proposed LC VCO reduces the amplitude variation 242 mV generated in the output signal of the conventional LC VCO to 47 mV. Furthermore, it improves the peak-to-peak time jitter from 8.71 ps to 931 fs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.3
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• pp.207-212
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• 2013

A new CMOS voltage-bias differential LC voltage-controlled oscillator (LC-VCO) with active source degeneration is proposed. The proposed degeneration technique preserves the quality factor of the LC-tank which leads to improvement in phase noise of VCO oscillators. The proposed VCO shows the high figure of merit (FOM) with large tuning range, low power, and small chip size compared to those of conventional voltage-bias differential LC-VCO. The proposed VCO implemented in 0.18-${\mu}m$ CMOS shows the phase noise of -118 dBc/Hz at 1 MHz offset oscillating at 5.03 GHz, tuning range of 12%, occupies 0.15 $mm^2$ of chip area while dissipating 1.44 mW from 0.8 V supply.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.11
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• pp.2480-2486
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• 2012

The design of low voltage LC-VCO(LC Voltage Controlled Oscillator) has been presented to optimize the phase noise and power consumption for the block of frequency synthesis to satisfy WCDMA system specification in this paper. The parameters for minimum phase noise has been obtained in the region of design, using the lines of the tuning range and the excess gain in the plane of the inductance and the transconductance of MOS transistor to compensate the loss of LC-tank. As a result of simulation, the phase noise characteristics is -113dBc/Hz for offset of 1MHz. The optimum designed LC-VCO has been fabricated using the process of 0.25um CMOS. As a result of measurement for fabricated chip, the phase noise characteristics is -116dBc/Hz for offset of 1MHz. The power consumption is 15mW, and Kvco is 370MHz/V.

• Journal of IKEEE
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• v.15 no.1
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• pp.29-36
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• 2011

Dithering scheme has been widely used to improve the resolution of DCO(Digitally Controlled Oscillator) in conventional ADPLLs(All Digital Phase Locked Loop). In this paper a new resolution improvement scheme is proposed where a simple DAC is employed to overcome the problems of dithering scheme. A 2.4GHz LC-based DCO has been designed in a $0.13{\mu}m$ CMOS process with an enhanced frequency resolution for wireless local area network applications. It has a frequency tuning range of 900MHz and a resolution of 58.8Hz. The frequencies are controled by varactors in coarse, fine, and DAC bank. The DAC bank consists of an inversion mode NMOS varactor. The other varactor banks consist of PMOS varactors. Each varactor bank is controlled by 8bit digital signal. The designed DCO exhibits a phase noise of -123.8dBc/Hz at 1MHz frequency offset. The DCO core consumes 4.2mA from 1.2V supply.

• Journal of Sensor Science and Technology
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• v.28 no.2
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• pp.121-126
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• 2019

The voltage-controlled oscillator is one of the fundamental building blocks that determine the signal quality and power consumption in RF transceivers for wireless sensor networks. Ring oscillators are attractive owing to their small form factor and multi-phase capability despite the relatively poor phase noise performance in comparison with LC oscillators. The phase noise of a ring oscillator can be improved by using a coupled structure that works at a lower frequency. This paper introduces a 2.4 GHz low-noise ring oscillator that consists of two 3-stage coupled ring oscillators. Each sub-oscillator operates at 800 MHz, and the multi-phase signals are combined to generate a 2.4 GHz quadrature output. The voltage-controlled ring oscillator designed in a 65-nm standard CMOS technology has a tuning range of 800 MHz and exhibits the phase noise of -104 dBc/Hz at 1 MHz offset. The power consumption is 13.3 mW from a 1.2 V supply voltage.

• The Journal of the Acoustical Society of Korea
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• v.16 no.4
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• pp.76-84
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• 1997

In this paper, one of the core components of a mobile communication system, VCO(Voltage Controlled Oscillator) IC is designed. The VCO IC was designed, have realized as LC turned oscillator using varicap. LC sinusoidal tuned oscillator generally requires external inductors and thus remainding circuit is implemneted in monolithic IC. The circuit is fabricated using an 15 mask IC process and has a die size of 1150um${\times}$780um. The tests showed that VCO was operated at frequencies in the regions between 880MHz-915MHz in the control voltage range of 1V to 3V at 5V supply voltage and as the power supply was varied from 4.5V to 5.5V, the frequency varied 425KHz/V. The VCO IC has frequency shift of 1.97MHz/T, carrier level of -7dBm and power consumption of 16.7mA. Also it has phase noise of -80dBc/Hz, offset at 50KHz and harmonic response of center frequency is -41dBm. For the future development of the transceiver 1 chip, the previously mentioned external devices need to be incorporated into Si MMIC.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.7
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• pp.23-29
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• 2012

The LC-based digitally controlled oscillator (LC-DCO), a key component of the all digital phase locked loop (ADPLL), is designed using $0.18{\mu}m$ RFCMOS process with 1.8 V supply. The NMOS core with double cross-coupled pair is chosen to realize wide tuning range, and the PMOS varactor pair that has small capacitance of a few aF and the capacitive degeneration technique to shrink the capacitive element are adopted to obtain the high frequency resolution. Also, the noise filtering technique is used to improve phase noise performance. Measurement results show the center frequency of 2.7 GHz, the tuning range of 2.5 GHz and the high frequency resolution of 2.9 kHz ~7.1 kHz. Also the fine tuning range and the current consumption of the core could be controlled by using the array of PMOS transistors using current biasing. The current consumption is between 17 mA and 26 mA at 1.8V supply voltage. The proposed DCO could be used widely in various communication system.