• Title/Summary/Keyword: LC design

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Output Filter Design of Voltage Source Inverter for CVCF System (CVCF용 VSI의 출력필터 설계)

  • 김재식;최재호
    • Proceedings of the KIPE Conference
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    • 1999.07a
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    • pp.287-290
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    • 1999
  • This paper describes an optimal design method of VSI output filter for CVCF system. The cost function is used for design, and all parameters are described in p.u(per unit) so that can be adapted to the change of CVCF rating. The capacitor current feedback scheme is proposed to control the damping ratio of the filter plant to meet the system more stable. This means that the LC resonance can be suppressed well in transient condition and can use the same control gains under the change of system capacity. The validity of the proposed method is well verified with the theoretical analysis and simulation results.

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A Study on the Block Cryptosystem Design with Variable Byte Operation (바이트 가변 연산기능을 가진 블록 암호시스템 설계에 관한 연구)

  • Lee, Seon-Keun
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.5
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    • pp.2311-2316
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    • 2011
  • With development of information communications and network environments security importance to the informations deepen as time goes. In this viewpoint, cryptosystem is developing but proportionally cracking and hacking technology is developing. Therefore in this paper we proposed and designed block cryptosystem with byte variable operation. Designed cryptosystem based on byte operation is safe than existed cryptosystem because it is not generate the fixed DC and LC characteristics. Additionally, proposed cryptosystem have high processing rate and authenticated operation. Therefore proposed cryptosystem is considered to many aid in the network fields.

Design of a Wide-Band CMOS VCO With Reduced Variations of VCO Gain and Frequency Steps for DTV Tuner Applications (VCO 이득 변화와 주파수 간격 변화를 줄인 DTV용 광대역 CMOS VCO 설계)

  • Ko, S.O.;Sim, S.M.;Sho, H.T.;Kim, C.K.;Yu, C.G.
    • Proceedings of the KIEE Conference
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    • 2008.10b
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    • pp.217-218
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    • 2008
  • Since the digital TV signal band is very wide ($54{\sim}806MHz$), the VCO used in the frequency synthesizer must also have a wide frequency tuning range. Multiple LC VCOs have been used to cover such wide frequency band. However, the chip area increases due to the increased number of integrated inductors. A general method for achieving both reduced VCO gain(Kvco) and wide frequency band is to use the switched-capacitor bank LC VCO. In this paper, a scheme is proposed to cover the full band using only one VCO. The RF VCO block designed using a 0.18um CMOS process consists of a wideband LC VCO with reduced variation of VCO gain and frequency steps. Buffers, divide-by-2 circuits and control logics the simulation results show that the designed circuit has a phase noise at 100kHz better than -106dBc/Hz throughout the signal band and consumes $9.5{\sim}13mA$ from a 1.8V supply.

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Development of a Adaptive Knowledge Base Object Model for Intelligent Tutoring System (지능형 교육 시스템을 위한 적응적 지식베이스 객체 모형 개발)

  • Kim Yong-Beom;Kim Yung-Sik
    • The KIPS Transactions:PartB
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    • v.13B no.4 s.107
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    • pp.421-428
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    • 2006
  • Intelligent Tutoring System(ITS), which offers individualized learning environment that consider many learners' variable, is realized by the effective alternative to take the place of domain expert. Accordingly, research on Learning Companion System(LC) is currently noticing. However, to develop LCS which applies effective interaction, it is necessary to combine several LCs, and personalized knowledge base have to be made first. Therefore, in this paper, we propose the 'Knowledge Base Object Medel', which is based on connectionist' in cognition structure, represents learner's knowledge to self-learnig object, and grows adaptive object by proprietor, verify the validity. This model lays the groundwork for design of personalized knowledge base, offers clue to development of adaptive ITS using knowledge base object.

Design of GSM BPF using Dissimilar LTCC Technology (이종적층 LTCC 기술을 이용한 GSM 대역 BPF 설계)

  • 고정호;이상노;육종관;박한규
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.14 no.9
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    • pp.931-935
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    • 2003
  • A multilayer two-stage LC bandpass filter using low-temperature cofired-ceramic(LTCC) is proposed in this paper. The proposed bandpass filter is composed of two ceramic substrates with different dielectric constant instead of single ceramic material from top to bottom layer. Inductive elements are designed in a low permitivity ceramic layer to reduce parasitic effects and loss, while capacitive elements are designed in a high permitivity ceramic layer for size reduction. The proposed filter has 950 MHz center &equency, 118 MHz tractional bandwidth, and 3.5 dB insertion loss. And, the total size of this filter is 2.5${\times}$2.5${\times}$l.4mm$^3$. The performance of filter is analyzed by changing coupling capacitance between each resonator.

High Power Factor Three Phase Rectifier for High Power Density AC/DC Conversion Applications

  • Cho, J.G.;Jeong, C.Y.;Baek, J.W.;Song, D.I.;Yoo, D.W.
    • Proceedings of the KIPE Conference
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    • 1998.10a
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    • pp.648-653
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    • 1998
  • The conventional three-phase rectifier with bulky LC output filter has been widely used in the industry because of its distinctive advantages over the active power factor correction rectifier such as simple circuit, high reliability, and low cost. Over than 0.9 power factor can be achieved, which is acceptable in most of industry applications. This rectifier, however, is not easy to use for high power density applications since the LC filter is bulky and heavy. To solve this problem, a new simple rectifier is presented in this paper. By eliminating the bulky LC filter from the conventional diode rectifier without losing most of the advantages of the conventional rectifier, very high power density power conversion with high power factor can be achieved. Operation principle and design considerations are illustrated and verified by Pspice simulation and experimental results from a prototype of 3.3 kW rectifier followed by 100KHz zero voltage switching full bridge PWM converter

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LC VCO using dual metal inductor in $0.18{\mu}m$ mixed signal CMOS process

  • Choi, Min-Seok;Jung, Young-Ho;Shin, Hyung-Cheol
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.503-504
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    • 2006
  • This paper presents the design and fabrication of a LC voltage-controlled oscillator (VCO) using 1-poly 6-metal mixed signal CMOS process. To obtain the high-quality factor inductor in LC resonator, patterned-ground shields (PGS) is placed under the symmetric inductor to reduce the effect from image current of resistive Si substrate. Moreover, due to the incapability of using thick top metal layer of which the thickness is over $2{\mu}m$, as used in many RF CMOS process, the structure of dual-metal layer in which we make electrically short circuit between the top metal and the next metal below it by a great number of via materials along the metal traces is adopted. The circuit operated from 2.63 GHz to 3.09 GHz tuned by accumulation-mode MOS varactor. The corresponding tuning range was 460 MHz. The measured phase noise was -115 dBc/Hz @ 1MHz offset at 2.63 GHz carrier frequency and the current consumption and the corresponding power consumption were about 2.6 mA and 4.68 mW respectively.

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A Study on the Output Noise Reduction of 3-Phase 3-Level Inverter (3상 NPC 3레벨 인버터 출력노이즈 저감에 관한 연구)

  • Kim, Soo-Hong;Jin, Kang-Hwan;Kim, Yoon-Ho
    • The Transactions of the Korean Institute of Power Electronics
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    • v.13 no.1
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    • pp.9-14
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    • 2008
  • Since they use the low switching frequency in multilevel inverter systems, they generate the high low frequency harmonic components. Generally, LC filter is used at the output terminal of inverter systems to solve this problem. But it causes a voltage drop at the output terminal by use of damping resistors, and causes the problem in which system efficiency decreases due to power loss of the damping resistor. In this paper, we proposed an output filter design method for NPC three-level inverter systems with low switching frequency. And we analyzed the efficiency of the proposed filter system, and the effectiveness of the proposed system is verified by simulation and experimental results.

Vascular Plants Distributed in Three Wetlands around Geumho River, Daegu Metropolitan City - Ganam Reservoir, Anshim Wetland and Jeomsae Swamp - (대구광역시 금호강 주변의 3개 습지에 분포하는 관속식물상 - 가남지, 안심습지, 점새늪을 중심으로 -)

  • You, Ju-Han
    • Journal of the Korean Society of Environmental Restoration Technology
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    • v.27 no.2
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    • pp.67-90
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    • 2024
  • The purpose of this study is to present the ecological data for conservation and management of three wetlands by surveying the vascular plants in Ganam reservoir, Ahnshim wetland and Jeomsae swamp. The whole taxa of vascular plants were 376 taxa including 90 families, 252 genera, 341 species, 7 subspecies, 24 varieties, 2 forms, 1 hybrid and 1 cultivar, and the planted species were 66 taxa including Ginkgo biloba and so on. The rare plants were 7 taxa including Euryale ferox(VU), Aristolochia contorta(LC), Koelreuteria paniculata(VU), Sagittaria trifolia(DD), Hydrocharis dubia(LC), Ottelia alismoides(LC) and Sparganium stoloniferum(VU). The Korean endemic plant was 1 taxon of Lespedeza maritima. In total, there were 21 taxa of floristic target species including 1 taxon of garde V, 2 taxa of grade IV, 6 taxa of grade III, 5 taxa of grade II and 7 taxa of grade I . The hydrophytes were 51 taxa including 36 taxa of emergent species, each 6 taxa of floating-leaved and submerged species and 3 taxa of free-floating species. The invasive alien plants were 79 taxa including 75 taxa of naturalized plants and 4 taxa of casual alien plant. The ecosystem disturbing species 6 taxa including Sicyos angulatus, Ambrosia artemisiifolia, Lactuca seriola, Symphyotrichum pilosum, Paspalum distichum and Humulus scandens.

Design of a 0.18$\mu$m CMOS 10Gbps CDR With a Quarter-Rate Bang-Bang Phase Detector (Quarter-Rate Bang-Bang 위상검출기를 사용한 0.18$\mu$m CMOS 10Gbps CDR 회로 설계)

  • Cha, Chung-Hyeon;Ko, Seung-O;Seo, Hee-Taek;Park, Jong-Tae;Yu, Chong-Gun
    • Journal of IKEEE
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    • v.13 no.2
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    • pp.118-125
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    • 2009
  • With recent advancement of high-speed, multi-gigabit data transmission capabilities, transmitters usually send data without clock signals for reduction of hardware complexity, power consumption, and cost. Therefore clock and data recovery circuits(CDR) become important to recover the clock and data signals and have been widely studied. This paper presents the design of 10Gbps CDR in 0.18$\mu$m CMOS process. A quarter-rate bang-bang phase detector is designed to reduce the power and circuit complexity, and a 4-stage LC-type VCO is used to improve the jitter characteristics. Simulation results show that the designed CDR consumes 80mW from a 1.8V supply, and exhibits a peak-to-peak jitter of 2.2ps in the recovered clock. The chip layout area excluding pads is 1.26mm$\times$1.05mm.

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