• KIPS Transactions on Computer and Communication Systems
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• v.8 no.5
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• pp.111-118
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• 2019

Recent graphic processing units (GPUs) provide high throughput by using powerful hardware resources. However, massive memory accesses cause GPU performance degradation due to cache inefficiency. Therefore, the performance of GPU can be improved by reducing thread parallelism when cache suffers memory contention. In this paper, we propose a dynamic warp scheduler which controls thread parallelism according to degree of cache contention. Usually, the greedy then oldest (GTO) policy for issuing warp shows lower parallelism than loose round robin (LRR) policy. Therefore, the proposed warp scheduler employs the LRR warp scheduling policy when Miss Status Holding Register(MSHR) utilization is low. On the other hand, the GTO policy is employed in order to reduce thread parallelism when MSHRs utilization is high. Our proposed technique shows better performance compared with LRR and GTO policy since it selects efficient scheduling policy dynamically. According to our experimental results, our proposed technique provides IPC improvement by 12.8% and 3.5% over LRR and GTO on average, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.10-12
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• 2002

사용자의 요구와 인터넷 어플리케이션의 발달로 규모가 큰 미디어 오브젝트의 수가 급증하고 있다. 따라서 네트워크 전송비용은 반드시 고려해야 하는 중요한 요소이다. 본 논문에서는 기존 프락시 캐시 교체 정책들을 분석하고, 이를 개선한 G-N 및 L-N 정책을 제안한다. 이것은 프락시 캐시 소프트웨어인 'Squid'에서 채택하고있는 GDSF와 LFU-DA 정책에 네트워크 전송 비용을 추가하여 확장한 알고리즘이다. 시뮬레이션을 통하여 기존의 알고리즘과 비교해 본 결과, 평균 응답 시간을 10%이상 감소시킬 수 있었으며, 추가로 드는 비용(Processing Overhead)은 3게 증가하지 아니 하였음을 확인하였다.

• Journal of Sensor Science and Technology
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• v.7 no.2
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• pp.124-130
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• 1998

High-speed 3D vision systems are essential for autonomous robot or vehicle control applications. In our study, a stereo vision process has been developed. It consists of three steps : extraction of edges in right and left images, matching corresponding edges and calculation of the 3D map. This process is implemented in a VME 150/40 Imaging Technology vision system. It is a modular system composed by a display, an acquisition, a four Mbytes image frame memory, and three computational cards. Programmable accelerator computational modules are running at 40 MHz and are based on TMS320C31 DSP with a $64{\times}32$ bit instruction cache and two $1024{\times}32$ bit internal RAMs. Each is equipped with 512 Kbytes static RAM, 4 Mbytes image memory, 1 Mbytes flash EEPROM and a serial port. Data transfers and communications between modules are provided by three 8 bit global video bus, and three local configurable pipeline 8 bit video bus. The VME bus is dedicated to system management. Tasks between DSPs are distributed as follows: two DSPs are used to edges detection, one for the right image and the other for the left one. The last processor computes the matching process and the 3D calculation. With $512{\times}512$ pixels images, this sensor generates dense 3D maps at a rate of about 1 Hz depending of the scene complexity. Results can surely be improved by using a special suited multiprocessors cards.

• Journal of KIISE:Information Networking
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• v.33 no.2
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• pp.156-164
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• 2006

The SCTP (Stream Control Transmission Protocol) implementation with the DAR (Dynamic Address Reconfiguration) extension is called the mSCTP (Mobile SCTP) that is proposed recently for mobility support in transport layer. The mSCTP does not satisfy short handover latency for real-time applications and it has no specific handover decision mechanisms. In this paper, we propose fast handover schemes for mobile nodes that are moving into different subnet using pre-acquisition RA (Router Advertisement) and L3 trigger for improving handover performance. Furthermore, we introduce three specific methods which are RA cache, FMIPv6 (Fast Handovers for Mobile IPv6) and dual interface and how proposed scheme can be interoperated with handover process respectively. Finally, we show two experimental results which are the mSCTP and the mSCTP using FMIPv6 on Linux platforms. Experimental results show that handover performance is improved with reducing the time of receiving RA which takes most of total handover latency.

• Journal of the Korea Computer Graphics Society
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• v.23 no.2
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• pp.1-10
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• 2017

A variety of filters are applied to improve the quality of noise and low resolution medical images. This is necessary to reduce the radiation dose of the patient and to improve the utilization of the conventional spherical imaging equipment. In the conventional method, it is common to perform filtering using the CPU of the PC. However, it is difficult to produce results in real time by applying various calculations and filters to high-resolution human images using only the CPU performance of a PC used in a hospital. In this paper, we analyze the structure and performance of Intel integrated GPU in CPU and propose a method to perform image filtering using OpenCL parallel processing function. By applying complex filters with high computational complexity to medical images, high quality images can be generated in real time.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.175-178
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• 2004

This paper describes a new IP address lookup algorithm using a binary search on multiple balanced trees stored in one memory. The proposed scheme has 3 different tables; a range table, a main table, and multiple sub-tables. The range table includes $2^8$ entries of 22 bits wide. Each of the main table and sub-table entries is composed of fields for a prefix, a prefix length, the number of sub-table entries, a sub-table pointer, and a forwarding RAM pointer. Binary searches are performed in the main table and the multiple sub-tables in sequence. Address lookups in our proposed scheme are achieved by memory access times of 11 in average, 1 in minimum, and 24 in maximum using 267 Kbytes of memory for 38.000 prefixes. Hence the forwarding table of the proposed scheme is stored into L2 cache, and the address lookup algorithm is implemented in software running on general purpose processor. Since the proposed scheme only depends on the number of prefixes not the length of prefixes, it is easily scaled to IPv6.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11B
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• pp.911-919
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• 2004

IP address lookup is one of the essential functions on internet routers, and it determines overall router performance. The most important evaluation factor for software-based IP address lookup is the number of the worst case memory accesses. Binary prefix tree (BPT) scheme gives small number of worst case memory accesses among previous software-based schemes. However the tree structure of BPT is normally unbalanced. In this paper, we propose weighted binary prefix tree (WBP) scheme which generates nearly balanced tree, through combining the concept of weight to the BPT generation process. The proposed WBPT gives very small number of worst case memory accesses compared to the previous software-based schemes. Moreover the WBPT requires comparably small size of memory which can be fit within L2 cache for about 30,000 prefixes, and it is rather simple for prefix addition and deletion. Hence the proposed WBPT can be used for software-based If address lookup in practical routers.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.41 no.2
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• pp.117-124
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• 2017

The performance of the colored Gauss-Seidel solver on CPU and GPU was investigated for the two- and three-dimensional heat conduction problems by using different mesh sizes. The heat conduction equation was discretized by the finite difference method and finite element method. The CPU yielded good performance for small problems but deteriorated when the total memory required for computing was larger than the cache memory for large problems. In contrast, the GPU performed better as the mesh size increased because of the latency hiding technique. Further, GPU computation by the colored Gauss-Siedel solver was approximately 7 times that by the single CPU. Furthermore, the colored Gauss-Seidel solver was found to be approximately twice that of the Jacobi solver when parallel computing was conducted on the GPU.