• Korean Journal of Computational Design and Engineering
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• v.13 no.3
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• pp.209-216
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• 2008

This paper presents a novel approach to design evaluation of portable consumer electronic (PCE) products using augmented reality (AR) based tangible interaction and functional behavior simulation. In the approach, the realistic visualization is acquired by overlaying the rendered image of a PCE product on the real world environment in real-time using computer vision based augmented reality. For tangible user interaction in an AR environment, the user creates input events by touching specified regions of the product-type tangible object with the pointer-type tangible object. For functional behavior simulation, we adopt state transition methodology to capture the functional behavior of the product into a markup language-based information model, and build a finite state machine (FSM) to controls the transition between states of the product based on the information model. The FSM is combined with AR-based tangible objects whose operation in the AR environment facilitates the realistic visualization and functional simulation of the product, and thus realizes faster product design and development. Based on the proposed approach, a product design evaluation system has been developed and applied for the design evaluation of various PCE products with highly encouraging feedbacks from users.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.4
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• pp.78-86
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• 1999

In this paper, a distributed arithmetic digital neural network with learning and testing phase implemented in a body has been studied. The proposed technique is based on the two facts; one is that the weighting coefficients adjusted will be stored in registers without shift, because input values or input patterns are not changed while learning and the other is that the input patterns stored in registers are not changed while testing. The proposed digital neural network is simulated by hardware description language such as VHDL and verified the performance that the neural network was applied to the recognition of seven-segment. To verify proposed neural networks, we compared the learning process of modified perceptron learning algorithm simulated by software with VHDL for 7-segment number recognizer. The results are as follows: There was a little difference in learning time and iteration numbers according to the input pattern, but generally the iteration numbers are 1000 to 10000 and the learning time is 4 to 200$\mu\textrm{s}$. So we knew that the operation of the neural network is learned in the same way with the learning of software simulation, and the proposed neural networks are properly operated. And also the implemented neural network can be built with less amounts of components compared with board system neural network.

• Journal of the Semiconductor & Display Technology
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• v.10 no.4
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• pp.7-13
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Semiconductor & Display Technology
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• v.10 no.3
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• pp.1-6
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• 2011

In this paper, the IC(Integrated Circuit) for multi-channel synchronous communication was designed by using FPGA and VHDL language. The existing chips for synchronous communication that has been used commercially are composed for one to two channels. Therefore, when communication system with three channels or more is made, the cost becomes high and it becomes complicated for communication system to be realized and also has very little buffer, load that is placed into Microprocessor increases heavily in case of high speed communication or transmission of high-capacity data. The designed IC was improved the function and performance of communication system and reduced costs by designing 8 synchronous communication channels with only one IC, and it has the size of transmitter/receiver buffer with 1024 bytes respectively and consequently high speed communication became possible. It was designed with a communication signal of a form various encoding. To detect errors of communications, the CRC-ITU-T logic and channel MUX logic was designed with hardware logics so that the malfunction can be prevented and errors can be detected more easily and input/output port regarding each communication channel can be used flexibly and consequently the reliability of system was improved. In order to show the performance of designed IC, the test was conducted successfully in Quartus simulation and experiment and the excellence was compared with the 85C3016VSC of ZILOG company that are used widely as chips for synchronous communication.

• Journal of the Korean Society of Marine Environment & Safety
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• v.21 no.4
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• pp.403-408
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• 2015

A text-based communication system has been developed with a communication function on AIS and display and input function on ECDIS as a way to complement voice communication. It features no linguistic error and is not affected by VHF restrictions on use and noise. The text communication system is designed to use messages for clear intentions and further improves convenience of users by using various UI through software. It works without additional hardware installation and modification and can transmit a sentence by selecting only via Message Banner Interface without keyboard input and furthermore has a advantage to enhance processing speed through its own message coding and decoding. It is determined as the most useful alternative to reduce language limitations and recognition errors of the user and solve the problem of various voice communications on VHF. In addition, it will help to prevent collisions between ships with decrease in VHF use, accurate communication and request of cooperation based on text at heavy traffic areas.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.8C
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• pp.1113-1124
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• 2004

In this paper, we proposed a hardware(H/W) structure which can compress and recontruct the input image in real time operation and implemented it into a FPGA platform using VHDL(VHSIC Hardware Description Language). All the image processing element to process both compression and reconstruction in a FPGA were considered each of them was mapped into H/W with the efficient structure for FPGA. We used the DWT(discrete wavelet transform) which transforms the data from spatial domain to the frequency domain, because use considered the motion JPEG2000 as the application. The implemented H/W is separated to both the data path part and the control part. The data path part consisted of the image processing blocks and the data processing blocks. The image processing blocks consisted of the DWT Kernel fur the filtering by DWT, Quantizer/Huffman Encoder, Inverse Adder/Buffer for adding the low frequency coefficient to the high frequency one in the inverse DWT operation, and Huffman Decoder. Also there existed the interface blocks for communicating with the external application environments and the timing blocks for buffering between the internal blocks The global operations of the designed H/W are the image compression and the reconstruction, and it is operated by the unit of a field synchronized with the A/D converter. The implemented H/W used the 69%(16980) LAB(Logic Array Block) and 9%(28352) ESB(Embedded System Block) in the APEX20KC EP20K600CB652-7 FPGA chip of ALTERA, and stably operated in the 70MHz clock frequency. So we verified the real time operation of 60 fields/sec(30 frames/sec).

• Progress in Medical Physics
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• v.14 no.1
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• pp.43-50
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• 2003

PACS mostly has been used in large scaled hospital due to expensive initial cost to set up the system. The network of PACS is independent of the others: network. The user's PC has to be connected physically to the network of PACS as well as the image viewer has to be installed. The web based mini-PACS can store, manage and search inexpensively a large quantity of radiologic image acquired in a hospital. The certificated user can search and diagnose the radiologic image using web browser anywhere Internet connected. The implemented Image viewer is a viewer to diagnose the radiologic image. Which support the DICOM standard and was implemented to use JAVA programming technology. The JAVA program language is cross-platform which makes easier upgrade the system than others. The image filter was added to the viewer so as to diagnose the radiologic image in detail. In order to access to the database, the user activates his web browser to specify the URL of the web based PACS. Thus, The invoked PERL script generates an HTML file, which displays a query form with two fields: Patient name and Patient ID. The user fills out the form and submits his request via the PERL script that enters the search into the relational database to determine the patient who is corresponding to the input criteria. The user selects a patient and obtains a display list of the patient's personal study and images.

• International Journal of Precision Engineering and Manufacturing
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• v.4 no.5
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• pp.27-33
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• 2003

G-code, another name of ISO6983, has been a popular commanding language for operating machine tools. This G-code, however, limits the usage of today's fast evolving high-performance hardware. For intelligent machines, the communications between machine and CAD/CAM departments become important, but the loss of information during generating G-code makes the production department isolated. The new standard for operating machine tools, named STEP-NC is just about to be standardized as ISO14649. As this new standard stores CAD/CAM information as well as operation commands of CNC machines, and this characteristic makes this machine able to exchange information with other departments. In this research, the new CNC machine operated by STEP-NC was built and tested. Unlike other prototypes of STEP-NC milling machines, this system uses the STEP-NC file in XML file form as data input. This machine loads information from XML file and deals with XML file structure. It is possible for this machine to exchange information to other databases using XML. The STEP-NC milling machines in this research loads information from the XML file, makes tool paths for two5D features with information of STEP-NC, and machines automatically without making G-code. All software is programmed with Visual $C^{++}$, and the milling machine is built with table milling machine, step motors, and motion control board for PC that can be directly controlled by Visual $C^{++}$ commands. All software and hardware modules are independent from each other; it allows convenient substitution and expansion of the milling machine. Example 1 in ISO14649-11 having the full geometry and machining information and example 2 having only the geometry and tool information were used to test the automatic machining capability of this system.

• Journal of KIISE:Computing Practices and Letters
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• v.10 no.5
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• pp.394-405
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• 2004

To make Web Services the real applications, the efficient mechanisms for Web Services discovery, Web Services composition and Web Services execution must be provided. Among these issues, especially, Web Services composition plays the key roles in Web Services applications that are loosely coupled and composed applications consisted of primitive Web Service components. In this paper we demonstrate a new Web Service composition approach using ontologies. We apply ontologies to describe Web Services information such as Web Services input/output parameters, pre conditions, post conditions and other necessary management information. In this paper, we also introduce Action ontology and Object ontology to describe the functional properties of Web Services These ontologies offer semantic description of Web Services functionalities beyond the limitation of the current WSDL. We can achieve semantic interoperabilities between heterogeneous Web Services in terms of conceptual processing and realize semantic services composition. We implement semantic Web Services composition system called Genie based on service description ontologies.

• Journal of Biosystems Engineering
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• v.7 no.2
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• pp.18-29
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• 1983

A low cost and versatile data acquisition system for the field and laboratory use was developed by using a single board microcomputer. Data acquisition system based on a Z80 microprocessor was built, tested and modified to obtain the present functional system. The microcomputer developed consists of 6 kB ROM, 5 kB RAM, 6-seven segment LED display, 16-Hex. key and 8 command key board. And it interfaces with an 8 channel, 12 bits A/D converter, a microprinter, EPROM programmer for 2716, and RS232C interface to transfer data between the system and HP3000 mini-computer manufactured by Hewlett Packard Co., A software package was also developed, tested, and modified for the system. This package included drivers for the AID converter, LED display, key board, microprinter, EPROM programmer, and RS232c interface. All of these programs were written in 280 assembler language and converted to machine codes using a cross assembler by HP3000 computer to the system during modifying stage by data transferring unit of this system, then the machine language wrote to the EPROM by this EPROM programmer. The results are summarized as follows: 1. Measuring program developed was able to control the measuring intervals, No. of channels used, and No. of data, where the maximum measuring speed was 58.8 microsec. 2. Calibration of the system was performed with triangle wave generated by a function generator. The results of calibration agreed well to the test results. 3. The measured data was able to be written into EPROM, then the EPROM data was compared with original data. It took only 75 sec. for the developed program to write the data of 2 kB the EPROM. 4. For the slow speed measurements, microprinter instead of EPROM programmer proved to be useful. It took about 15 min. for microprinter to write the data of 2 kB. 5. Modified data transferring unit was very effective in communicating between the system and HP3000 computer. The required time for data transferring was only 1~2 min. 6. By using DC/DC converting devices such as 78-series, 79-series. and TL497 IC, this system was modified to convert the only one input power sources to the various powers. The available power sources of the system was DC 7~25 V and 1.8 A.