• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.41-48
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• 2018

This paper describes the systems engineering development process for the Departure from Nucleate Boiling Ratio (DNBR) algorithm using FPGA. Current Core Protection Calculator System (CPCS) requirement and DNBR logic are analyzed in the reverse engineering phase and the new FPGA based DNBR algorithm is designed in the re-engineering phase. FPGA based DNBR algorithm is developed by VHSIC Hardware Description Language (VHDL) in the implementation phase and VHDL DNBR software is verified in the software Verification & Validation phase. Test cases are developed to perform the software module test for VHDL software modules. The APR 1400 simulator is used to collect the inputs data in 100%, 75%, and 50% reactor power condition. Test input signals are injected to the software modules following test case tables and output signals are compared with the expected test value. Minimum DNBR value from developed DNBR algorithm is validated by KEPCO E&C CPCS development facility. This paper summarizes the process to develop the FPGA-based DNBR calculation algorithm using systems engineering approach.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.281-286
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• 2007

Road traffic accidents kill more than one million people a year. ESCC represents a new device, that hasn't any analogue. This embedded system, heats the car glasses, when it's needed, that makes more safety driving. It's build on Atmega128L CPU, using high-performance EEPROM CPLD ATF1504AS. Source code was written in C language. Algorithm of work was written by dew-point table. This system is not only clearing the glass from condensation, but averts condensation. ESCC began working, when input information became close to dew-point table information. Thankful this device, field of view is more widely, that increase safety level.

• Proceedings of the KSPS conference
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• 2007.05a
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• pp.41-44
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• 2007

In this paper, we introduce a system in which car navigation scenario is plugged multimodal interface based on multimodal middleware. In map-based system, the combination of speech and pen input/output modalities can offer users better expressive power. To be able to achieve multimodal task in car environments, we have chosen SCXML(State Chart XML), a multimodal authoring language of W3C standard, to control modality components as XHTML, VoiceXML and GPS. In Network Manager, GPS signals from navigation software are converted to EMMA meta language, sent to MultiModal Interaction Runtime Framework(MMI). Not only does MMI handles GPS signals and a user's multimodal I/Os but also it combines them with information of device, user preference and reasoned RDF to give the user intelligent or personalized services. The self-simulation test has shown that middleware accomplish a navigational multimodal task over multiple users in car environments.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.6
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• pp.220-229
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• 1996

We presetn sytem-level simulation methodology as well as environment setup established for CDMA digtial cellular mobile station in an effort to verify CDMA modem ASIC design. To make the system-level simulation feasible, behavioral modeling of a microcontroller was first carried out with VHDL. In addition, models written in C language were also developed to provide ASIC with realistic input data. Finally, the netlist of CDMA modem ASIC was loaded on the a hardware accelerator, which was interfaced with VHDL simulator, and ismulation was performed by excuting the actual CDMA call processing software. Simulation resutls thus obtained were confirmed by comparing them with the emulation resutls from the actual system constructed on hardware modeler. these methods were proved to be effective in both discovering in advance malfunctions when embedded in the system or design errors of ASIC and reducing simulation time by a factor of as much as 20 in case of simulation at gate-level.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.657-660
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• 2002

In this paper, the FFT processor for power measurement using VHDL (Very high-speed integrated circuit Hardware Description Language) is discussed. The proposed system relies on the FFT algorithm to compute real and reactive power. The advantage of system is that harmonic analysis is carried out on a period of the Input signal. The proposed system is based on FFT Processor which is designed using VHDL. In the design of FFT processor, $radix-2^2$ is adopted to reduce several complex multipliers for twiddle factor. And this processor adopt pipeline structure. Therefore, the system Is able to have both high hardware efficiency and high performance.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.3
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• pp.288-291
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• 2004

This paper proposes an intelligent search modeling using avatar agent. This system consists of some modules such as agent interface, agent management, preprocessor, interface machine. Core-Symbol Database and Spell Checker are related to the preprocessor module and Interface Machine is connected with Best Aggregate Designer. Our avatar agent system does the indexing work that converts user's natural language type sentence to the proper words that is suitable for the specific branch information retrieval. Indexing is one of the preprocessing steps that make it possible to guarantee the specialty of user's input and increases the reliability of the result. It references a database that consists of synonym and specific branch dictionary. The resulting symbol after indexing is used for draft search by the internet search engine. The retrieval page position and link information are stored in the database. We experimented our system with the stock market keyword SAMSUNG_SDI, IBM, and SONY and compared the result with that of Altavista and Google search engine. It showed quite excellent results.

• Journal of the Korean BIBLIA Society for library and Information Science
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• v.21 no.2
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• pp.81-96
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• 2010

This study aimed to suggest metadata elements for online reference resource systems based on users' perceptions. We surveyed librarians in four types of libraries, asking them indicate the need for each of 17 metadata elements. The survey results were compared to the current data input rates of the system, which has been operating for the past two years. Based on both the respondent data and current data input rates, we suggested that title, description, subject, creator, type, identifier, language, coverage, location, and tag elements must be included in the system as the metadata elements for online reference resources. n addition, the input rates of creator and copyright were 20.20% and 18.30%, respectively, but the respondents answered that these items were needed 82.15% and 82.77%, respectively. Therefore, these two items are necessary as metadata elements. On the other hand, the data input rates of type, source, date, relation, and contribution were less than 3%, but almost 70% of respondents answered that all these items were needed. So further research should be performed to determine whether or not these items are needed for online reference resource systems.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.3
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• pp.116-123
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• 2003

This paper deals with an experimental study for on-line monitoring the performance of a universal motor for vacuum cleaner. Performance tests are conducted on the PC-based virtual instrumentation system designed using the graphical programming language LabVIEW. The proposed monitoring system is capable of performing real time measurement functions, including data acquisition, display, and analyses in the time and frequency domains, as well as data archiving. The measured mechanical and iron loss, voltage, current, input power, power factor, torque, and efficiency characteristics are presented as function of speed.

• Journal of Biosystems Engineering
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• v.17 no.1
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• pp.65-78
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• 1992

When using a computer vision system for a measurement, the geometrically distorted input image usually restricts the site and size of the measuring window. A geometrically distorted image caused by the image sensing and processing hardware degrades the accuracy of the visual measurement and prohibits the arbitrary selection of the measuring scope. Therefore, an image calibration is inevitable to improve the measuring accuracy. A calibration process is usually done via four steps such as measurement, modeling, parameter estimation, and compensation. In this paper, the efficient error calibration technique of a geometrically distorted input image was developed using a neural network. After calibrating a unit pixel, the distorted image was compensated by training CMLAN(Cerebellar Model Linear Associator Network) without modeling the behavior of any system element. The input/output training pairs for the network was obtained by processing the image of the devised sampled pattern. The generalization property of the network successfully compensates the distortion errors of the untrained arbitrary pixel points on the image space. The error convergence of the trained network with respect to the network control parameters were also presented. The compensated image through the network was then post processed using a simple DDA(Digital Differential Analyzer) to avoid the pixel disconnectivity. The compensation effect was verified using known sized geometric primitives. A way to extract directly a real scaled geometric quantity of the object from the 8-directional chain coding was also devised and coded. Since the developed calibration algorithm does not require any knowledge of modeling system elements and estimating parameters, it can be applied simply to any image processing system. Furthermore, it efficiently enhances the measurement accuracy and allows the arbitrary sizing and locating of the measuring window. The applied and developed algorithms were coded as a menu driven way using MS-C language Ver. 6.0, PC VISION PLUS library functions, and VGA graphic functions.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.11
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• pp.152-161
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• 1996

This paper descrisbes the implementation of a 20D DCT that can be used for video conference, JPEG, and MPEG-related applications. The implemented DCT consists of two 1-D DCTs and a transposed memory between them, and uses ROM-based multipliers instead of conventional ones. As the system bit length, the minimum bit length that satisfies the accuracy specified by the ITU standard H.261 was chosen through the simulations using the C language. The proposed design uses a dual port RAM for the transposed memory, and processes two bits of input-pixel data simultaneously t ospeed up addition process using two sets of ROMs. The basic system architecture was designed using th Synopsys schematic editor, and internal modules were described in VHDL and synthesized to logic level after simulation. Then, the compass silicon compiler was used to create the final lyout with 0.8um CMOS libraries, using the standard cell approach. The final layout contains about 110, 000 transistors and has a die area of 4.68mm * 4.96mm, and the system has the processing speed of about 50M pixels/sec.