• Journal of Korean Home Economics Education Association
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• v.13 no.3
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• pp.119-130
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• 2001

The purpose of this research is to discover how Practical Reasoning Home Economics Instruction(PRHEI) applied to food and nutrition units would impact on the morality of female high school students. The research sample was drawn from the two freshman classes of \"M\" High School far Girls. located in the Pusan area. One classroom of 50 students was used as the test group and the other of 47 as the control group for the total of 97 students. Measuring the intellectual and behavioral morality scores followed the pre-post test design under which the PRHEI was administered to the test group during the period of eight weeks in a semester. Whereas the control group received the conventional lecture-oriented instruction during the same period. The effects of PRHEI on morality were measured using the system developed in 1972 by Ontario Institute for Studies in Education. and translated by Kim. Ahn-Jung in 1982. The system developed by Yang. Byung-Han in 1994 was utilized to measure the behavioral morality score. In analyzing the collected data. SPSS/WIN was used to generate means standard deviation and t-test. The research findings are as follows : First. The students who have been taught under the PRHEI score higher on the intellectual morality scale than the control group receiving the lecture-oriented instruction. Second. The test croup students do not show any notable differences from the control group students receiving the lecture-oriented approach on the behavioral morality scale; however, the former do show statistically significant differences from the latter in the sub-factor of honesty scoring higher means over the control group.

• Convergence Security Journal
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• v.16 no.7
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• pp.173-180
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• 2016

There has been a growing interest in automation of factories in the country. And, the development in this regard has been actively attempted. In particular, on the basis of the "innovation 3.0 strategy of manufacturing industry", interest in the smart of the manufacturing plant of small and medium-sized enterprises has increased rapidly. As well as policy for building smart plant, technical, seeking a strategic approach. But, in order to introduce such a smart plant or factory automation systems, manufacturing plant security with vulnerability and personal information protection problems, it should always be top priority there. Accordingly, we provide the applicable lightweight secure protocols in RFID communication. It is a wireless communication technology that is most often introduced for factory automation. Our proposed lightweight secure protocol in this study, less the number of calculations in comparison with the existing public key-based and the symmetric key encryption algorithm. And it is fast in compare with the existing protocol. Furthermore, we design that it system can support to low power consumption and small consume the memory size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.11A
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• pp.1206-1212
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• 2007

International Civil Aviation Organization(ICAO) adopted VOR(Very high frequency Omni-Range) as an international standard air navigation system in 1949 and recommended every country to make use of it in formulating air route and guiding take-off and landing of an aircraft. VOR is quite a useful navigation system so that more than 2,000 VORs are currently installed all over the world including 39 in the Republic of Korea; however, VOR signal could be easily affected by its circumstance like a mountainous area because it provides navigation information to an aircraft through AM and FM of VHF carrier. There are two types of VOR which are defined according to a design methode. Therefore this study intends to investigate which type of VOR is suitable for mountainous area. For that purpose, the performance of each CVOR and DVOR is measured and analyzed by using an aircraft equipped with measuring instruments. The analyzed result will be applied and utilized in selecting the VOR type, so it could be a feasible solution of problem related to the VOR relocation due to its insufficient performance in the future.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.368-368
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• 2008

Ion implantation has been widely developed during the past decades to become a standard industrial tool. To comply with the growing needs in ion implantation, innovative technology for the control of ion beam parameters is required. Beam current, beam profile, ion fractions are of great interest when uniformity of the implant is an issue. Especially, it is important to measure the spatial distribution of beam power and also the energy distribution of accelerated ions. This energy distribution is influenced by the proportion of mass for ion in the plasma generator(ion source) and by charge exchange and dissociation within the accelerator structure and also by possible collective effects in the neutralizer which may affect the energy and divergence of ions. Hydrogen atom has been the object of a good study to investigate the energy distribution. Hydrogen ion sources typically produce multi-momentum beams consisting of atomic ion ($H^+$) and molecular ion ($H_2^+$ and $H_3^+$). In the beam injector, the molecular ions pass through a charge-exchanges gas cell and break up into atomic with one-half (from $H_2^+$) or one-third (from $H_3^+$) according to their accelerated energy. Burrell et al. have observed the Doppler shifted lines from incident $H^+$, $H_2^+$, and $H_3^+$ using a Doppler shift spectroscopy. Several authors have measured the proportion of mass for hydrogen ion and deuterium using an ion source equipped with a magnetic dipole filter. We developed an ion implanter with 50-KeV and 20-mA ion source and 100-keV accelerator tube, aiming at commercial uses. In order to measure the proportion of mass for ions, we designed a filter system which can be used to measure the ion fraction in any type of ion source. The hydrogen and helium ion species compositions are used a filter system with the two magnets configurations.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.3
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• pp.40-47
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• 2010

In this study, we investigated the performance of real-time QRS complex detection algorithm in physio-module for echocardiography. The performance of QRS detection module in echocardiography was evaluated according to international standard, EC-13 and we compared with commercialized physio-module with QRS complex detection. In this study, we can get performance of QRS complex detection, pacer pulse detection, Tall t-wave rejection and arrhythmia detection within EC-13's criteria and we can get improved QRS trigger delay time and baseline wondering rejection times in compared with commercialized physio-module.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.72-78
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• 2009

This paper proposes a low phase noise ring voltage controlled oscillator(VCO) with a standard $0.13{\mu}m$ CMOS process for PLL circuit using the VCO-gain-controlled Delay cell. The proposed Delay cell architecture with a active resistor using a MOS transistor. This method can reduced a VCO gain so that improve phase noise. And, Delay cell consist of Wide-Swing Cascode current mirror, Positive Latch and Symmetric load for low phase noise. The measurement results demonstrate that the phase noise is -119dBc/Hz at 1MHz offset from 1.9GHz. The VCO gain and power dissipation are 440MHz/V and 9mW, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.15-23
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• 2009

This paper presents a novel high-speed, low-complexity flexible 128/64-point $radix-2^4$ FFT/IFFT processor for the applications in high-throughput MIMO-OFDM systems. The high radix multi-path delay feed-back (MDF) FFT architecture provides a higher throughput rate and low hardware complexity by using a four-parallel data-path scheme. The proposed processor not only supports the operation of FFT/IFFT in 128-point and 64-point but can also provide a high data processing rate by using a four-parallel data-path scheme. Furthermore, the proposed design has a less hardware complexity compared with traditional 128/64-point FFT/IFFT processors. Our proposed processor has a high throughput rate of up to 560Msample/s at 140MHz while requiring much smaller hardware expenditure satisfying IEEE 802.11n standard requirements.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.31-41
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• 2009

IEEE 802.11e proposed by IEEE 802.11 working group to guarantee QoS has contention based EDCA and contention free based HCCA. HCCA, a centralized polling based mechanism of 802.11e, needs a scheduling algorithm to allocate the network resource efficiently. The existing standard scheduler, however, is inefficient to support for QoS guarantee for real-time service having VBR traffic. To improve these limit, in this paper, we First, we propose priority polling algorithm which additionally considers the size of MSI and TXOP based on EDD algorithm to increase number of QSTAs. We also propose a dual token bucket TXOP allocation algorithm to reduce congestion caused by stations which enters network with considerable delay variance. TSPEC parameters, Maximum Burst Size (MBS) and Peak Data Rate (PR), are applied to design depth and token generation rate of two buckets. Simulation results show that the proposed algorithm has much higher performance compared with reference and SETT-EDD scheduler in terms of throughput and delay.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.3
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• pp.21-29
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• 2012

This paper presents optimized searching technique to improve the performance of H.264/AVC. By using the proposed forward and backward searching algorithm, redundant cycles of latency for data reordering can be removed. Furthermore, in order to reduce the total number of execution cycles of CAVLC encoder, early termination mode and two stage pipelined architecture are proposed. The experimental result shows that the proposed architecture needs only 36.0 cycles on average for each $16{\times}16$ macroblock encoding. The proposed architecture improves the performance by 57.8% than that of previous designs. The proposed CAVLC encoder was implemented using Verilog HDL and synthesized with Magnachip $0.18{\mu}m$ standard cell library. The synthesis result shows that the gate count is about 17K with 125Mhz clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.6
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• pp.68-73
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• 2008

In this paper, we propose watermark algorithm called TDWA(Time-Division Watermarking Algorithm) and we applied the proposed algorithm to H.264 video coding standard. We establish that a proposed algorithm is applied to H.264 baseline profile CODEC. The proposed algorithm inserts a watermark into the spatial domain of several frames. We can easily insert strong and invisible watermarks into original pictures using this method. For verification of the proposed algorithm we design hardware core using Verilog-HDL and Excalibur for JM 8.7 code with hardware & software co-simulation. As a result of verification, the PSNR between watermarked pictures and original pictures are more than 60dB and we found the watermark is kept more than 80% after encoding of H.264/AVC with quantization parameter of 28 in baseline profile.