• ETRI Journal
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• v.28 no.1
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• pp.31-44
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• 2006

In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

• Journal of Korean Institute of Industrial Engineers
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• v.37 no.4
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• pp.382-389
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• 2011

Salesperson Monitoring System (SMS) is geographic based information system that supports business auditing, sales area coordinating and customer management for each salesperson. Conventional SMSs focus mainly on the monitoring or logging functions, i.e., a salesperson locating or moving trail tracking. However, the schedules have been planned by human planner, and they have rarely been managed with a software system like SMS. In this paper, a mixed integer programming model for a salesperson routing schedule is provided. Then, 2-phase Genetic Algorithm (GA) is proposed to make salesperson routing schedule. Experimental results show a validity of the proposed method.

• ETRI Journal
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• v.45 no.4
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• pp.627-635
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• 2023

In vehicular edge computing (VEC) networks, the rapid expansion of intelligent transportation and the corresponding enormous numbers of tasks bring stringent requirements on timely task offloading. However, many tasks typically appear within a short period rather than arriving simultaneously, which makes it difficult to realize effective and efficient resource scheduling. In addition, some key information about tasks could be learned due to the regular data collection and uploading processes of sensors, which may contribute to developing effective offloading strategies. Thus, in this paper, we propose a model that considers the deterministic demand of multiple tasks. It is possible to generate effective resource reservations or early preparation decisions in offloading strategies if some feature information of the deterministic demand can be obtained in advance. We formulate our scenario as a 0-1 programming problem to minimize the average delay of tasks and transform it into a convex form. Finally, we proposed an efficient optimal offloading algorithm that uses the interior point method. Simulation results demonstrate that the proposed algorithm has great advantages in optimizing offloading utility.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.3B
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• pp.171-182
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• 2003

In this paper, we propose an efficient and simple fair queueing algorithm, called Minimum Possible Virtual Start Time Fair Queueing (MPSFQ), which has O(1) complexity for the virtual time computation while it has good delay and fairness properties. The key idea of MPSFQ is that it has an easy system virtual time recalibration method while it follows a rate-proportional property. MPSFQ algorithm recalibrates system virtual time to the minimum possible virtual start time of all backlogged sessions. We will show our algorithm has good delay and fairness properties by analysis.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.2
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• pp.1-6
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• 2021

In this paper, an efficient implementation of AES encryption algorithm is presented for CCTV image security using C# language. In this approach, an efficient S-Box is first designed for reducing the computation time which is required in each round process of AES algorithm, and then an CCTV image security system is implemented on the basis of this algorithm on a composite field GF(((22)2)2). In addition, the shared S-Box structure is designed for realizing the minimized memory space, which is used in each round transformation and key scheduling processes. Through performance evaluation, it was confirmed that the proposed method is more efficient than the existing method. The proposed CCTV system in C# language using Visual studio 2010.

• Ocean Systems Engineering
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• v.3 no.3
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• pp.237-255
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• 2013

In many applications, Remotely Operated Vehicles (ROVs) are required to be capable of course keeping, depth keeping, and height keeping. The ROV must be able to resist time-variant external forces and moments or frequent manipulate changes in some specified circumstances, which require the control system meets high precision, fast response, and good robustness. This study introduces a Fuzzy-Incomplete Derivative Ahead-PID (FIDA-PID) control system for a 500-meter ROV with four degrees of freedom (DOFs) to achieve course, depth, and height keeping. In the FIDA-PID control system, a Fuzzy Gain Scheduling Controller (FGSC) is designed on the basis of the incomplete derivative ahead PID control system to make the controller suitable for various situations. The parameters in the fuzzy scheme are optimized via many cycles of trial-and-error in a 10-meter-deep water tank. Significant improvements have been observed through simulation and experimental results within 4-DOFs.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.7
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• pp.875-880
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• 2019

A RC4 stream cipher is widely used for security applications such as IEEE 802.11 WEP, IEEE 802.11i TKIP and so on, because it can be simply implemented to dedicated circuits and achieve a high-speed encryption. RC4 is also used for systems with limited resources like IoT, but there are performance limitations. RC4 consists of two stages, KSA and PRGA. KSA performs initialization and randomization of S-box and K-box and PRGA produces cipher texts using the randomized S-box. In this paper, we initialize the S-box and K-box in the randomization of the KSA stage to reduce the initialization delay. In the randomization, we use clusters to process swap operation between elements of S-box in parallel and can generate two cipher texts per clock. The proposed RC4 cipher hardware can initialize S-box and K-box without any delay and achieves about 2 times to 6 times improvement in KSA randomization and key stream generation.

• Journal of Communications and Networks
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• v.18 no.2
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• pp.227-237
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• 2016

Data collection is a key function for wireless sensor networks. There has been numerous data collection scheduling algorithms, but they fail to consider the deep and complex relationship among network lifetime, sink aggregated information and sample cycle for wireless sensor networks. This paper gives the upper bound on the sample period under the given network topology. An optimal schedule algorithm focusing on aggregated information named OSFAI is proposed. In the schedule algorithm, the nodes in hotspots would hold on transmission and accumulate their data before sending them to sink at once. This could realize the dual goals of improving the network lifetime and increasing the amount of information aggregated to sink. We formulate the optimization problem as to achieve trade-off among sample cycle, sink aggregated information and network lifetime by controlling the sample cycle. The results of simulation on the random generated wireless sensor networks show that when choosing the optimized sample cycle, the sink aggregated information quantity can be increased by 30.5%, and the network lifetime can be increased by 27.78%.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.3
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• pp.427-433
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• 2002

This paper describes a design of cryptographic processor that implements the AES(Advanced Encryption Standard) block cipher algorithm "Rijndael". To achieve high throughput rate, a sub-pipeline stage is inserted into the round transformation block, resulting that the second half of current round function and the first half of next round function are being simultaneously operated. For area-efficient and low-power implementation, the round block is designed to share the hardware resources in encryption and decryption. An efficient scheme for on-the-fly key scheduling, which supports the three master-key lengths of 128-b/192-b/256-b, is devised to generate round keys in the first sub-pipeline stage of each round processing. The cryptoprocessor designed in Verilog-HDL was verified using Xilinx FPGA board and test system. The core synthesized using 0.35-${\mu}{\textrm}{m}$ CMOS cell library consists of about 25,000 gates. Simulation results show that it has a throughput of about 520-Mbits/sec with 220-MHz clock frequency at 2.5-V supply.-V supply.

• Journal of Communications and Networks
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• v.18 no.3
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• pp.420-428
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• 2016

In this paper, we investigate the scheduling and power allocation for coordinated multi-point transmission in downlink long term evolution advanced (LTE-A) systems, where orthogonal frequency division multiple-access is used. The proposed scheme jointly optimizes user selection, power allocation, and modulation and coding scheme (MCS) selection to maximize the weighted sum throughput with fairness consideration. Considering practical constraints in LTE-A systems, the MCSs for the resource blocks assigned to the same user need to be the same. Since the optimization problem is a combinatorial and non-convex one with high complexity, a low-complexity algorithm is proposed by separating the user selection and power allocation into two subproblems. To further simplify the optimization problem for power allocation, the instantaneous signal-to-interference-plus-noise ratio (SINR) and the average SINR are adopted to allocate power in a single cell and multiple coordinated cells, respectively. Simulation results show that the proposed scheme can improve the average system throughput and the cell-edge user throughput significantly compared with the existing schemes with limited feedback.