• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.81-87
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• 1989

A cellular array multiplier for performing the multiplication of two elements in the finite field GF($2^m$) is presented in this paper. This multiplier is consisted of three operation part ; the multiplicative operation part, the modular operation part, and the primitive irreducible polynomial operation part. The multiplicative operation part and the modular operation part are composed by the basic cellular arrays designed AND gate and XOR gate. The primitive iirreducible operation part is constructed by XOR gates, D flip-flop circuits and a inverter. The multiplier presented here, is simple and regular for the wire routing and possesses the properties of concurrency and modularity. Also, it is expansible for the multiplication of two elements in the finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.30-37
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• 2007

An exponentiation in $GF(2^m)$ is a basic operation for several algorithms used in cryptography, digital signal processing, error-correction code and so on. Existing hardware implementations for the exponentiation operation organize by Right-to-Left method since a merit of parallel circuit. Our paper proposes a polynomial exponentiation structure with a trinomial that is organized by Left-to-Right method and that utilizes a weakly dual basis. The basic idea of our method is to decrease time delay using precomputation tables because one of two inputs in the Left-to-Right method is fixed. Since $T_{sqr}$ (squarer time delay) + $T_{mul}$(multiplier time delay) of ow method is smaller than $T_{mul}$ of existing methods, our method reduces time delays of existing Left-to-Right and Right-to-Left methods by each 17%, 10% for $x^m+x+1$ (irreducible polynomial), by each 21%, 9% $x^m+x^k+1(1, by each 15%, 1% for $x^m+x^{m/2}+1$.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.12 no.2
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• pp.45-52
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• 2002

In this contributions, we propose a new MSB(most significant bit) algorithm based on AOP(All One Polynomial) and two parallel semi-systolic architectures to computes $AB^2$over finite field $GF(2^m)$. The proposed architectures are based on standard basis and use the property of irreducible AOP(All One Polynomial) which is all coefficients of 1. The proposed parallel semi-systolic architecture(PSM) has the critical path of $D_{AND2^+}D_{XOR2}$ per cell and the latency of m+1. The modified parallel semi-systolic architecture(WPSM) has the critical path of $D_{XOR2}$ per cell and has the same latency with PSM. The proposed two architectures, PSM and MPSM, have a low latency and a small hardware complexity compared to the previous architectures. They can be used as a basic architecture for exponentiation, division, and inversion. Since the proposed architectures have regularity, modularity and concurrency, they are suitable for VLSI implementation. They can be used as a basic architecture for algorithms, such as the Diffie-Hellman key exchange scheme, the Digital Signature Algorithm(DSA), and the ElGamal encryption scheme which are needed exponentiation operation. The application of the algorithms can be used cryptosystem implementation based on elliptic curve.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.8
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• pp.35-45
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• 1999

In this paper, the addition and the multiplicative algorithm of two polynomials over finite field $GF(p^m)$ are presented. The 4-valued arithmetic processor of the serial input-parallel output modular structure on $GF(4^3)$ to be performed the presented algorithm is implemented by current mode CMOS. This 4-valued arithmetic processor using current mode CMOS is implemented one addition/multiplication selection circuit and three operation circuits; mod(4) multiplicative operation circuit, MOD operation circuit made by two mod(4) addition operation circuits, and primitive irreducible polynomial operation circuit to be performing same operation as mod(4) multiplicative operation circuit. These operation circuits are simulated under $2{\mu}m$ CMOS standard technology, $15{\mu}A$ unit current, and 3.3V VDD voltage using PSpice. The simulation results have shown the satisfying current characteristics. The presented 4-valued arithmetic processor using current mode CMOS is simple and regular for wire routing and possesses the property of modularity. Also, it is expansible for the addition and the multiplication of two polynomials on finite field increasing the degree m and suitable for VLSI implementation.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.25 no.2
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• pp.241-251
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• 2015

In public-key cryptographic system based on finite field arithmetic, it is very important to challenge for implementing high speed operation. In this paper, we focused on 8-bit ATmega128 processor and concentrated on enhancing efficiency of reduction operation which uses irreducible polynomial $f(x)=x^{271}+x^{207}+x^{175}+x^{111}+1$ and $f(x)=x^{193}+x^{145}+x^{129}+x^{113}+1$. We propose optimized reduction algorithms which are designed to reduce repeated memory accesses by calculating final reduced values of Fast reduction. There are 53%, 55% improvement when proposed algorithm is implemented using assembly language, compare to previous Fast reduction algorithm.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.6
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• pp.24-30
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• 2003

This study focuses on the arithmetical methodology and hardware implementation of low system-complexity A $B^2$＋C operator over GF(2$^{m}$ ) using the irreducible AOP of degree m. The proposed parallel-in parallel-out operator is composed of CS, PP, and MS modules, each can be established using the array structure of AND and XOR gates. The proposed multiplier is composed of (m＋1)$^2$ 2-input AND gates and (m＋1)(m＋2) 2-input XOR gates. And the minimum propagation delay is $T_{A}$ ＋(1＋$\ulcorner$lo $g_2$$^{m}$ $\lrcorner$) $T_{x}$ . Comparison result of the related A $B^2$＋C operators of GF(2$^{m}$ ) are shown by table, It reveals that our operator involve more lower circuit complexity and shorter propagation delay then the others. Moreover, the interconnections of the out operators is very simple, regular, and therefore well-suited for VLSI implementation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.49-54
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• 2008

In cryptosystems based on finite fields, a modular multiplication operation is the most crucial part of finite field arithmetic. Also, in multipliers with resource constrained environments, bit-serial output structures are used in general. This paper proposes two efficient bit-serial output multipliers with the polynomial basis representation for irreducible trinomials. The proposed multipliers have lower time complexity compared to previous bit-serial output multipliers. One of two proposed multipliers requires the time delay of $(m+1){\cdot}MUL+(m+1){\cdot}ADD$ which is more efficient than so-called Interleaved Multiplier with the time delay of $m{\cdot}MUL+2m{\cdot}ADD$. Therefore, in elliptic curve cryptosystems and pairing based cryptosystems with small characteristics, the proposed multipliers can result in faster overall computation. For example, if the characteristic of the finite fields used in cryprosystems is small then the proposed multipliers are approximately two times faster than previous ones.

• Journal for History of Mathematics
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• v.32 no.4
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• pp.159-173
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• 2019

In this paper, we examine the brief history of the ring of four almonds regarding Mesopotamian mathematics, and present reasons why the Omar Khayyam's triangle, a special right triangle in a ring of four almonds, was essential for artisans due to its unique pattern. We presume that the ring of four almonds originated from a point symmetry figure given two concentric squares used in the proto-Sumerian Jemdet Nasr period (approximately 3000 B.C.) and a square halfway between two given concentric squares used during the time of the Old Akkadian period (2340-2200 B.C.) and the Old Babylonian age (2000-1600 B.C.). Artisans tried to create a new intricate pattern as almonds and 6-pointed stars by subdividing right triangles in the pattern of the popular altered Old Akkadian square band at the time. Therefore, artisans needed the Omar Khayyam's triangle, whose hypotenuse equals the sum of the short side and the perpendicular to the hypotenuse. We presume that artisans asked mathematicians how to construct the Omar Khayyam's triangle at a meeting between artisans and mathematicians in Isfahan. The construction of Omar Khayyam's triangle requires solving an irreducible cubic polynomial. Omar Khayyam was the first to classify equations of integer polynomials of degree up to three and then proceeded to solve all types of cubic equations by means of intersections of conic sections. Omar Khayyam's triangle gave practical meaning to the type of cubic equation $x^3+bx=cx^2+a$. The work of Omar Khayyam was completed by Descartes in the 17th century.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.43 no.1 s.307
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• pp.1-8
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• 2006

This thesis proposes Arithmetic Shift Register(ASR) which can be used as pseudo random number generator. Arithmetic Shift. Register is defined as progression that multiplies random number D , not 0 or 1 at initial value which is not 0, and it is represented as ASR-D in this thesis. Irreducible polynomial that t which makes $'D^k=1'$ satisfies uniquely as $'t=2^n-1'$ over. $GF(2^n)$ is the characteristic polynomial of ASR-D , and the cycle of Arithmetic Shift Register has maximum cycle as $'2^n-1'$. Galois Linear Feedback Shift Register corresponds to ASR-2-1. Therefore, Arithmetic Shift Register proposed in this thesis generalizes Galois Linear Feedback Shift Register. Linear complexity of ASR-D over$GF(2^n)$ is $'n{\leq}LC{\leq}\frac{n^2+n}{2}'$ and in comparison with existing Linear Feedback Shift Register stability is high. The Software embodiment of arithmetic shift register proposed in this thesis is efficient than that of existing Linear Shift Register and hardware complexity is equal. Arithmetic shift register proposed in this thesis can be used widely in various fields such as cipher, error correcting codes, Monte Carlo integral, and data communication etc along with existing linear shift register.

• Journal of IKEEE
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• v.7 no.1 s.12
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• pp.9-15
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• 2003

An optimized finite-field multiplier is proposed for encryption and error correction devices. It is based on a modified Linear Feedback Shift Register (LFSR) which has lower power consumption and smaller area than prior LFSR-based finite-field multipliers. The proposed finite field multiplier for GF(2n) multiplies two n-bit polynomials using polynomial basis to produce $z(x)=a(x)^*b(x)$ mod p(x), where p(x) is a irreducible polynomial for the Galois Field. The LFSR based on a serial multiplication structure has less complex circuits than array structures and hybrid structures. It is efficient to use the LFSR structure for systems with limited area and power consumption. The prior finite-field multipliers need 3${\cdot}$m flip-flops for multiplication of m-bit polynomials. Consequently, they need 6${\cdot}$m latches because one flip-flop consists of two latches. The proposed finite-field multiplier requires only 4${\cdot}$m latches for m-bit multiplication, which results in 1/3 smaller area than the prior finite-field multipliers. As a result, it can be used effectively in encryption and error correction devices with low-power consumption and small area.