• Title/Summary/Keyword: Inverter Circuit

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Stacked LTCC Band-Pass Filter for IEEE 802.11a (IEEE 802.11a용 적층형 LTCC 대역통과 여파기)

  • Lee Yun-Bok;Kim Ho-Yong;Lee Hong-Min
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.2 s.93
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    • pp.154-160
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    • 2005
  • Microwave Otters are essential device in modem wireless systems. A compact dimension BPF(Band-pass Filter) for IEEE 802.11a WLAN service is realized using LTCC multi-layer process. To extrude 2-stage band-pass equivalent circuit, band-pass and J-inverter transform applied to Chebyshev low-pass prototype filter. Because parallel L-C resonator is complicate and hard to control the inductor characteristics in high frequency, the shorted $\lambda/4$ stripline is selected for the resonator structure. The passive element is located in the different layers connected by conventional via structure and isolated by inner GND. The dimension of fabricated stacked band-pass filter which is composed of six layers, is $2.51\times2.27\times1.02\;mm^3$. The measured filter characteristics show the insertion loss of -2.25 dB, half-power bandwidth of 220 MHz, attenuation at 5.7 GHz of -32.25 dB and group delay of 0.9 ns at 5.25 GHz.

A 125 MHz CMOS Delay-Locked Loop with 64-phase Output Clock (64-위상 출력 클럭을 가지는 125 MHz CMOS 지연 고정 루프)

  • Lee, Pil-Ho;Jang, Young-Chan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2012.10a
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    • pp.259-262
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    • 2012
  • This paper describes a delay-locked loop (DLL) that generates a 64-phase clock with the operating frequency of 125MHz. The proposed DLL use a $4{\times}8$ matrix-based delay line to improve the linearity of a delay line. The output clock with 64-phase is generated by using a CMOS multiplex and a inverted-based interpolator from 32-phase clock which is the output clock of the $4{\times}8$ matrix-based delay line. The circuit for an initial phase lock, which is independent on the duty cycle ratio of the input clock, is used to prevent from the harmonic lock of a DLL. The proposed DLL is designed using a $0.18-{\mu}m$ CMOS process with a 1.8 V supply. The simulated operating frequency range is 40 MHz to 200 MHz. At the operating frequency of a 125 MHz, the worst phase error and jitter of a 64-phase clock are +11/-12 ps and 6.58 ps, respectively.

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Carrier Comparison PWM for Voltage Control of Vienna Rectifier (비엔나 정류기의 전압제어를 위한 반송파 비교 PWM)

  • Yoon, Byung-Chul;Kim, Hag-Wone;Cho, Kwan-Yuhl
    • Journal of the Korea Academia-Industrial cooperation Society
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    • v.12 no.10
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    • pp.4561-4568
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    • 2011
  • In this paper, carrier comparison PWM method for voltage control of Vienna rectifier is discussed. In general, in industrial and communications applications, the two-level rectifier is used. However, this two-level rectifier has the limit of high THD and low efficiency. So, the studies of three-level rectifier has been carried out so far, and the Vienna rectifier circuit is the representative. The space vector pulse width modulation(SVPWM) method is generally used for Vienna rectifier, in which voltage vectors and duration time are calculated from the voltage reference. However, this method require very sophisticated and complex calculations, so realizing this method by software is very difficult. To overcome this disadvantage, simple carrier comparison PWM method for Vienna rectifier is proposed which is modified from the carrier comparison method for 3 level inverter. Furthermore, to verify the usefulness of the Vienna rectifier carrier comparison PWM the simulation and experiment are carried out.

A High Voltage Poorer Supply for Electrostatic Precipitator with Superimposing Voltage Pulse on DC Source (펄스 및 직류 중첩형 전기집진기용 고전압 전원장치 개발 연구)

  • Kim, Jong-Soo;Rim, Geun-Hie;Lee, Sung-Jin;Kim, Seung-Min;Cho, Chang-Ho
    • The Transactions of the Korean Institute of Electrical Engineers B
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    • v.50 no.12
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    • pp.624-630
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    • 2001
  • The trend of the regulations on environmental issues are getting tight. Responding to this trend new technologies such as moving electrodes, wide pitch and pulsed power supply are also introduced in the electrostatic precipitator(EP) systems. The introduction of wide pitch and moving electrodes enhances the system performance of the EPs by improving air-flow and by improving the ash reentrainment on rapping. The power supplies for the EPs developed up to date include thyristor-based dc or intermittent type, SMPS(switching mode power supply) type and the pulsed-power supply type. The use of the pulsed ones is known to improve dust-collecting efficiency of high resistivity ash and reduces back corona occurrence in the collecting plate. There are two kinds of pulsed-power supplies; one with pulsed transformers and the other with direct dc switching devices. The latter uses rotary spark gap switches or semiconductor switches. Both have the merits and demerits: the spark gap switches are simple and robust but has short life time, hence, high maintenance cost, whereas the semiconductor switches have long life time but are costly. In this study, A high voltage power supply with superimposing voltage pulse on dc source was developed for EPs. This study describes circuit topology, operating principle of the scheme, and analysis of experimental results on Dong-Hae Power Plant. The pulsed power supply consists of a variable dc power supply with ratings of 60kV, 800mA and pulse generator which is made of high voltage thyristor-diode switch strings, an LC resonant tank and a blocking inductor. The pulse generator generates variable pulse-voltage up to 70kV using a high frequency resonant inverter with a variable dc source. Two prototypes were built and tested on 250MW DongHae power plant to verify the possibility of the commercial use and the normal operation in the transient states.

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Improvement of Naval Combat System UPS under Abnormal Transients (비정상 과도상태에서의 해군 전투체계 UPS 개선)

  • Kim, Sung-Who;Choi, Han-Go
    • Journal of the Institute of Convergence Signal Processing
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    • v.19 no.3
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    • pp.97-103
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    • 2018
  • This paper addresses an improved naval combat UPS(Uninterruptable Power Supply) system under abnormal transients. Previously, thermistor and varistor elements were used to cope with transient overvoltage and overcurrent, however the UPS was frequently unavailable because it was vulnerable to abnormal transient voltage generated during system operation. In order to overcome this problem and protect UPS system, this paper proposes an input power cut-off circuit that detects the initial input power and abnormal transient voltage generated during operation, improvement of power control sequence, and a method to prevent malfunction of an inverter and CPU. The UPS system implementing the proposed method was simulated by input power variable test using programmable AC/DC generator, and finally validated its reliability and stability through field tests by mounting on multifunctional console of naval combat system.

Evaluation of Flexible Complementary Inverters Based on Pentacene and IGZO Thin Film Transistors

  • Kim, D.I.;Hwang, B.U.;Jeon, H.S.;Bae, B.S.;Lee, H.J.;Lee, N.E.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.154-154
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    • 2012
  • Flexible complementary inverters based on thin-film transistors (TFTs) are important because they have low power consumption and high voltage gain compared to single type circuits. We have manufactured flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The circuits were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. The characteristics of TFTs and inverters were evaluated at different bending radii. The applied strain led to change in voltage transfer characteristics of complementary inverters as well as source-drain saturation current, field effect mobility and threshold voltage of TFTs. The switching threshold voltage of fabricated inverters was decreased with increasing bending radius, which is related to change in parameters of TFTs. Throughout the bending experiments, relationship between circuit performance and TFT characteristics under mechanical deformation could be elucidated.

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Hybrid complementary circuits based on organic/inorganic flexible thin film transistors with PVP/Al2O3 gate dielectrics

  • Kim, D.I.;Seol, Y.G.;Lee, N.E.;Woo, C.H.;Ahn, C.H.;Ch, H.K.
    • Proceedings of the Korean Vacuum Society Conference
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    • 2011.02a
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    • pp.479-479
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    • 2011
  • Flexible inverters based on complementary thin-film transistor (CTFTs) are important because they have low power consumption and other advantages over single type TFT inverters. In addition, integrated CTFTs in flexible electronic circuits on low-cost, large area and mechanically flexible substrates have potentials in various applications such as radio-frequency identification tags (RFIDs), sensors, and backplanes for flexible displays. In this work, we introduce flexible complementary inverters using pentacene and amorphous indium gallium zinc oxide (IGZO) for the p-channel and n-channel, respectively. The CTFTs were fabricated on polyimide (PI) substrate. Firstly, a thin poly-4-vinyl phenol (PVP) layer was spin coated on PI substrate to make a smooth surface with rms surface roughness of 0.3 nm, which was required to grow high quality IGZO layers. Then, Ni gate electrode was deposited on the PVP layer by e-beam evaporator. 400-nm-thick PVP and 20-nm-thick ALD Al2O3 dielectric was deposited in sequence as a double gate dielectric layer for high flexibility and low leakage current. Then, IGZO and pentacene semiconductor layers were deposited by rf sputter and thermal evaporator, respectively, using shadow masks. Finally, Al and Au source/drain electrodes of 70 nm were respectively deposited on each semiconductor layer using shadow masks by thermal evaporator. Basic electrical characteristics of individual transistors and the whole CTFTs were measured by a semiconductor parameter analyzer (HP4145B, Agilent Technologies) at room temperature in the dark. Performance of those devices then was measured under static and dynamic mechanical deformation. Effects of cyclic bending were also examined. The voltage transfer characteristics (Vout- Vin) and voltage gain (-dVout/dVin) of flexible inverter circuit were analyzed and the effects of mechanical bending will be discussed in detail.

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A Design on High Frequency CMOS VCO for UWB Applications (UWB 응용을 위한 고주파 CMOS VCO 설계 및 제작)

  • Park, Bong-Hyuk;Lee, Seung-Sik;Choi, Sang-Sung
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.2 s.117
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    • pp.213-218
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    • 2007
  • In this paper, we propose the design and fabrication on high frequency CMOS VCO for DS-UWB(Direct-Sequence Ultra-WideBand) applications using 0.18 ${\mu}m$ process. The complementary cross-coupled LC oscillator architecture which is composed of PMOS, NMOS symmetrically, is designed for improving the phase noise characteristic. The resistor is used instead of current source that reduce the 1/f noise of current source. The high-speed buffer is needed for measuring the output characteristic of VCO using spectrum analyzer, therefore the high-speed inverter buffer is designed with VCO. A fabricated core VCO size is $340{\mu}m{\times}535{\mu}m$. The VCO is tunable between 7.09 and 7.52 GHz and has a phase noise lower than -107 dBc/Hz at 1-MHz offset over entire tuning range. The measured harmonic suppression is 32 dB. The VCO core circuit draws 2.0 mA from a 1.8 V supply.

Development of EQM(Engineering Qualified Model) Local Oscillator far Ka-band Satellite Transponder (Ka-band위성 중계기용 국부발진기의 우주인증모델(EQM) 개발)

  • 류근관;이문규;염인복;이성팔
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.15 no.4
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    • pp.335-344
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    • 2004
  • A low phase noise EQM(Engineering Qualified Model) LO(Local Oscillator) has been developed for Ka-band satellite transponder. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is also designed using a high impedance inverter coupled with dielectric resonator to improve the phase noise performances out of the loop bandwidth. The mechanical analysis fur housing and the thermal analysis fur circuit board are achieved. This EQM LO is applied to Ka-band satellite transponder of EQM level after environmental experiments for space application. The LO has the harmonic suppression characteristics above 52 ㏈c and requires low power consumption under 1.3 watts. The phase noise characteristics are exhibited as -101.33 ㏈c/㎐ at 10 ㎑ offset frequency and -114.33 ㏈c/㎐ at 100 ㎑ offset frequency, with the output power of 14.0 ㏈m${\pm}$0.17 ㏈ over the temperature range of -15∼+65$^{\circ}C$.

Power Consumption Change in Transistor Ratio of Ring Voltage Controlled Oscillator (링 전압 제어 발진기의 트랜지스터 비율에 따른 소모 전력 변화)

  • Moon, Dongwoo;Shin, Hooyoung;Lee, Milim;Kang, Inseong;Lee, Changhyun;Park, Changkun
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.27 no.2
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    • pp.212-215
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    • 2016
  • In this paper, a 5.08 GHz Ring Voltage Controlled Oscillator(Ring VCO) was implemented using $0.18{\mu}m$ standard CMOS technology. The proposal Ring VCO is 3-stage structure. This research confirmed that the each stage's different transistor size ratio influence the current change and alter power consumption consequentially. This circuit is formed to control the current thereby adding the Current Mirror and to tune the frequency by supplying control voltage. It has an 65.5 %(1.88~5.45 GHz) tuning range. The measured output power is -0.30 dBm. The phase noise is -87.50 dBc/Hz @1 MHz offset with operating frequency of 5.08 GHz fundamental frequency. The total power consumption of Ring VCO is 31.2 mW with 2.4 V supply voltage.