• Information Display
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• v.12 no.2
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• pp.32-39
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• 2011

• Steel and Composite Structures
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• v.17 no.2
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• pp.159-172
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• 2014

A finite element model with the consideration of damage initiation and evolution has been developed for the analysis of the dynamic response of a composite sandwich panel subject to low velocity impact. Typical damage modes including fiber breakage, matrix crushing and cracking, delamination and core crushing are considered in this model. Strain-based Hashin failure criteria with stiffness degradation mechanism are used in predicting the initiation and evolution of intra-laminar damage modes by self-developed VUMAT subroutine. Zero-thickness cohesive elements are adopted along the interface regions between the facesheets and the foam core to simulate the initiation and propagation of delamination. A crushable foam core model with volumetric hardening rule is used to simulate the mechanical behavior of foam core material at the plastic state. The time history curves of contact force and the core collapse area are obtained. They all show a good correlation with the experimental data.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.4
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• pp.39-50
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• 2011

In this paper, we presents a CDR circuit for $2^{nd}$-generation AiPi+, one of the Intra-panel Interface. The speed of the proposed clock and data recovery is increased to 1.25 Gbps compared with that of AiPi+. The DLL-based CDR architecture is used to generate the multi-phase clocks. We propose the simple scheme for frequency detector (FD) to mitigate the harmonic-locking and reduce the complexity. In addition, the duty cycle corrector that limits the maximum pulse width is used to avoid the problem of missing clock edges due to the mismatch between rising and falling time of VCDL's delay cells. The proposed CDR is implemented in 0.18 um technology with the supply voltage of 1.8 V. The active die area is $660\;{\mu}m\;{\times}\;250\;{\mu}m$, and supply voltage is 1.8 V. Peak-to-Peak jitter is less than 15 ps and the power consumption of the CDR except input buffer, equalizer, and de-serializer is 5.94 mW.