• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.10
• /
• pp.141-151
• /
• 1994

this paper describes the design and implementation of a RISC processor for embedded control systems. This RISC processor integrates a register file, a pipelined execution unit, a FPU interface, a memory interface, and an instruction prefetcher. Its characteristics include both single cycle executions of most instructions in a 2 phase 20 MHz frequency and the worst case interrupt latency of 7 cycles with the vectored interrupt handling that makes it possible to be applicable to the real time processing system. For efficient handling of multi-cycle instructions, data stationary hardwired control scheme equippedwith cycle counter was used. This chip integrates about 139K transistors and occupies 9.1mm$\times$9.1mm in a 1.0um DLM CMOS technology. The power dissipation is 0.8 Watts from a 5V supply at 20 MHz operation.

• Journal of Korea Multimedia Society
• /
• v.12 no.9
• /
• pp.1309-1315
• /
• 2009

This research goal of developing and producing a tool that finds security weakness that may happen when a usual program is executed. The analyzing tool for security weakness has the major functions as follows. In case that a part of anticipated security weakness are in execution, it traces a machine language to a part in execution. And Monitoring System calls and DLL(API) calls when a program is in execution. The result of this study will enable to contribute to use as educational materials for security service in companies and related agencies and to prevent from hacking of external information invaders in the final analysis.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
• /
• v.14 no.5
• /
• pp.385-393
• /
• 2021

This study proposes a multi-core-based controller design for an ESC(Electronic Stability Control) system in an automotive multi-core processor. Considering the architectures of an automotive multi-core processor and an ESC system, the overall execution time has been optimized for multi-core platforms. The function module assignment, synchronization between cores, and memory assignment for core-dependent variables in automotive multi-core systems are evaluated. The ESC controller comprising five function modules is used herein. Based on the proposed design, the single-core controller is extended to multi-core controllers. Using multi-core optimization methods, such as function module assignment, semaphore, interrupt awakening, and variable assignment over cores, the ESC system is redesigned to a multi-core controller. Experimental results reveal that the execution time for the multi-core processor is reduced by 59.7% compared with that for the single-core processor.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.22 no.10
• /
• pp.2136-2149
• /
• 1997

This paper describes RISC core that has been designed for embedded and protable applications such as PDA or PCS. This RISC processor offers low power consumption and fast context switching. Processor performance is improved by using conditional instruction execution, block data transfer instruction, and multiplication instruction. This architecture is based on RISC principles. The processor adopts 3-stage instruction execution pipeline and has achieved single cycle execution using a 2-phase 40MHz clock. This results in a high instruction throughput and real-time interrupt response. This chip is implemented with $0.6{\mu}m$ triple metal CMOS technology and consists of about 88K transistors. The estimated power dissipation is 179mW.

• Journal of Korea Society of Industrial Information Systems
• /
• v.14 no.2
• /
• pp.8-15
• /
• 2009

The need for ASP(Application Service Provider) has evolved from the increasing costs of specialized software that have far exceeded the price rage of small to medium sized businesses. There are a lot of technologies that make ASP possible, and software streaming service is one of them Software streaming is a method for overlapping transmission and execution of stream-enabled software. The stream-enabled software is able to run on a device even while the transmission/streaming of the software may still be in progress. Thus, a user does not have to wait for the completion of the software's download prior to starting to execute the software. In this paper, we suggest the new concept of software streaming system implement using the PageFault Interrupt Routine Hooking. As it is able to efficiently manage application, we do not have to install the entire software. In addition, we can save hardware resources by using it because we load basic binaries without occupying the storage space of the hardware.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.12
• /
• pp.13-23
• /
• 1996

In tis paper we researched the implementation methodology and techniques for the high real-time responsive operating system of an ISDN PABX system. The operating system we developed takes a high role as a dedicated real-time operating system for PABX systems. It provides the functions and synchronization, interprocessor communication, interrupt processing, and data I/O processing. And also it provides lots of real-time processing functions for supproting various real-time applications. Finally, we evaluated the performance by measuring the best, the average, and the worst-case execution time of all functions implemented in this real-time operating system.

• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.105-108
• /
• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.12
• /
• pp.9-19
• /
• 1997

This paper describes the design and FPGA implementation of a system control unit within a multiprocessor chip which can be used as a node processor ina massively parallel processing (MPP) caches, memory management units, a bus unit and a system control unit. Major functions of the system control unit are locking/unlocking of the shared variables of protected access, synchronization of instruction execution among four integer untis, control of interrupts, generation control of processor's status, etc. The system control unit was modeled in very high level using verilog HDL. Then, it was simulated and verified in an environment where trap handler and external interrupt controller were added. Functional blocks of the system control unit were changed into RTL(register transfer level) model and synthesized using xilinx FPGA cell library in synopsys tool. The synthesized system control unit was implemented by Xilinx FPGA chip (XC4025EPG299) after timing verification.

• Journal of KIISE:Computing Practices and Letters
• /
• v.13 no.5
• /
• pp.271-281
• /
• 2007

Real-time support of embedded OS is not optional, but essential in contemporary embedded systems. In order to achieve these system#s real-time property, it is crucial that schedulability analysis for tasks having its property have been accomplished before system execution. Acquiring Worst-Case Execution Time(WCET) of task is a core part of schedulability analysis. Because traditional WCET tools analyze only its estimation of application task(i.e. program), it is not considered that application tasks are affected by scheduling primitives(e.g. scheduler, interrupt service routine, etc.) of OS when it schedules them. In this paper, we design and implement WCET analysis tool which deliberates on scheduling primitives of system using embedded Linux widely used in embedded OSes. This tool can estimate either WCET of normal application programs or corresponding primitives which have an influence on schduling property in embedded Linux kernel. Therefore, precision of estimation about schedulability analysis is improved. We develop this tool as Eclipse#s plug-in to work properly in any platform and support convenient interface or functionality for user.

• Journal of the Korean Society of Manufacturing Process Engineers
• /
• v.19 no.8
• /
• pp.81-87
• /
• 2020

A stable rotational-to-linear motion transformation structure using a driving mechanism with 2 degrees of freedom was developed for an orthogonal mechanism to prevent the interference of each axis in 2D motion. In this mechanism, a step motor was used for precise position control. This structure was developed to maneuver workparts in micro particle blast machining experiments. To determine the real-time performance of micro particle blast machining, the control, input, and output were operated simultaneously and precise position control was implemented, using a timer interrupt with multiple execution codes. The two step motors obtained precise position control by removing backlash with a ball-screw mechanism. The device has menu-type control codes for user-friendliness, and real-time sequence control was simultaneously adopted for user control input.