• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.2
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• pp.1073-1083
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• 2015

As an empirical study focused on how transactive memory concept influence the four processes of knowledge growth, this study aimed at explaining the function of transactive memory in the dynamic process of knowledge growth. To verify the research model, this study carried out a path analysis of 130 team memebers and as a result, part of the team transactive memory measurements does affect the knowledge growth. Consequentially, transactive memory especially based on team level, is relevant with knowledge growth. According to team level, this study targeted at the team members, and by adopting the team transactive memory concept in Cognitive Psycology, theoretically explained and analysed how to approach personal knowledge in internal organizations. To accelerate the knowledge process, the work should be modified collaboratively by trusting the team members' duty relations more than specialized knowledge. Furthermore, managers had better assign team members the work where they can make the most of their personal knowledge, and this study presented that the whole team performance could be improved by doing that.

• Dementia and Neurocognitive Disorders
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• v.22 no.4
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• pp.148-157
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• 2023

Background and Purpose: Episodic memory is a system that receives and stores information about temporally dated episodes and their interrelations. Our study aimed to investigate the relevance of episodic memory to time perception, with a specific focus on simultaneity/order judgment. Methods: Experiment 1 employed the simultaneity judgment task to discern differences in time perception between patients with mild cognitive impairment or dementia, and age-matched normals. A mathematical analysis capable of estimating subjects' time processing was utilized to identify the sensory and decisional components of temporal order and simultaneity judgment. Experiment 2 examined how differences in temporal perception relate to performance in temporal order memory, in which time delays play a critical role. Results: The temporal decision windows for both temporal order and simultaneity judgments exhibited marginal differences between patients with episodic memory impairment, and their healthy counterparts (p = 0.15, t(22) = 1.34). These temporal decision windows may be linked to the temporal separation of events in episodic memory (Pearson's ρ = -0.53, p = 0.05). Conclusions: Based on our findings, the frequency of visual events accumulated and encoded in the working memory system in the patients' and normal group appears to be approximately (5.7 and 11.2) Hz, respectively. According to the internal clock model, a lower frequency of event pulses tends to result in underestimation of event duration, which phenomenon might be linked to the observed time distortions in patients with dementia.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.224-240
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• 1996

It is common sense for at least one or more levels of cache memory to be used in these day's computer systems. In this paper, the impact of the internal cache memory organization on the performance of the computer is investigated by using a simulator program, which is wirtten by authors and run on SUN SPARC workstation, with several real execution, with several real execution trace files. 280 cache organizations have been simulated using n-way set associative mapping and LRU(Least Recently Used) replacement algorithm with write allocation policy. As a result, 16-way setassociative cache is the best configuration, and when we select 256KB cache memory and 64 byte line size, the bus traffic ratio was decreased compared to that of the noncache system so that a single bus could support almost 7 processors without any delay and degradationof high ratio(hit ratio was 99.21%). The smaller the line size we choose, the little lower hit ratio we can get, but the more processors can be supported by a single bus(maximum 18 processors). Therefore, using a proper cache memory organization can make a single bus structure be able to support multiple processors without any performance degradation.

• Smart Structures and Systems
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• v.14 no.5
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• pp.765-784
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• 2014

In comparison with conventional shape memory actuated structures, antagonistic shape memory alloy (SMA) actuators permits a fully reversible two-way response and higher response frequency. However, excessive internal stress could adversely reduce the stroke of the actuators under repeated use. The two-way shape memory effect might further decrease the range of the recovered strain under actuation of an antagonistic SMA actuator unless additional components (e.g., spring and stopper) are added to regain the overall actuation capability. In this paper, the performance of all four possible types of SMA actuation schemes is investigated in detail with emphasis on five key properties: recovered strain, cyclic degradation, response frequency, self-sensing control accuracy, and controllable maximum output. The testing parameters are chosen based on the maximization of recovered strain. Three types of these actuators are antagonistic SMA actuators, which drive with two active SMA wires in two directions. The antagonistic SMA actuator with an additional pair of springs exhibits wider displacement range, more stable performance under reuse, and faster response, although accurate control cannot be maintained under force interference. With two additional stoppers to prevent the over stretch of the spring, the results showed that the proposed structure could achieve significant improvement on all five properties. It can be concluded that, the last type actuator scheme with additional spring and stopper provide much better applicability than the other three in most conditions. The results of the performance analysis of all four SMA actuators could provide a solid basis for the practical design of SMA actuators.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.142-150
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• 2021

Open-channel SSD is a new type of Solid-State Disk (SSD) that improves the garbage collection overhead and write amplification due to physical constraints of NAND flash memory by exposing the internal structure of the SSD to the host. However, the host-level Flash Translation Layer (FTL) provided for open-channel SSDs in the current Linux kernel consumes host memory excessively because it use page-level mapping table to translate logical address to physical address. Therefore, in this paper, we implemente a selective mapping table loading scheme that loads only a currently required part of the mapping table to the mapping table cache from SSD instead of entire mapping table. In addition, to increase the hit ratio of the mapping table cache, filesystem information and mapping table access history are utilized for cache replacement policy. The proposed scheme is implemented in the host-level FTL of the Linux kernel and evaluated using open-channel SSD emulator. According to the evaluation results, we can achieve 80% of I/O performance using the only 32% of memory usage compared to the previous host-level FTL.

• Transactions of Materials Processing
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• v.33 no.5
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• pp.330-340
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• 2024

The martensitic Ni-Ti shape memory alloys(SMA) can achieve a two-way shape memory effect (TWSME) through thermomechanical training/cycling. In this study, the surface of Ni-Ti SMA sheets was treated by depositing a certain number of titanium (Ti) powder layers using a selective laser meling (SLM) process to enhance TWSME. The results showed that a unique TWSME of approximately 12% with good stability was achieved after 100 training cycles when the optimum number of five Ti layers was deposited. A larger HAZ and lower cooling rate pushed more Ti particles into the grains rather than the grain boundaries, providing more time for Ti to react with NiTi to form Ti-rich intergranular Ti2Ni(Ox) precipitates. This resulted in further hindering of dislocation movement within the grains and the generation of internal stress fields required for attaining a larger TWSME. With an increase in the number of Ti-deposited layers, there was no noticeable reduction in the one-way shape memory effect (OWSME) through the initial cycling. This was due to the high residual tensile stress caused by the lower thermal expansion of the Ti layer compared to the Ni-Ti sheet.

• The Journal of Internal Korean Medicine
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• v.29 no.3
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• pp.608-620
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• 2008

Objectives : This study investigated the protective effects of the water extracts of Chongmyung-tang, Polygalae Radix, and Acori Graminei Rhizoma in an in vivo Alzheimer's disease (AD) mouse model. Methods : Memory impairment was induced by an intraventricular injection of $A{\beta}25-35$ peptides and subsequently Chongmyung-tang, Polygalae Radix, or Acori Graminei Rhizoma extract were administered orally for 14days. Results : In the water maze task, Chongmyung-tang, Polygalae Radix, and Acori Graminei Rhizoma extracts improved learning ability during the acquisition period and significantly increased memory scores during the retention period versus $A{\beta}-injected$ controls. Furthermore, the toxicity of $A{\beta}25-35$ on hippocampus was assessed immunohistochemically (Tau, MAP2, TUNEL, Bax) and by in vitro study. Chongmyung-tang, Polygalae Radix, and Acori Graminei Rhizoma demonstrated significant neuroprotective effects against oxidative damage and apoptotic cell death of hippocampal neurons damaged by $A{\beta}25-35$. Conclusions : These results suggested that Chongmyung-tang, Polygalae Radix and Acori Graminei Rhizoma extract improve memory impairment and reduce Alzheimer's dementia via anti-apoptotic effects and by modulating the expressions of Tau and MAP2 protein in the hippocampus.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.22 no.6
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• pp.99-105
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• 2022

This paper deals with the problem of appropriately allocating multiple processors arriving at the ready queue to the block in the user space of the main memory is divided into blocks of variable size at compilation time. The existing allocation methods, first fit(FF), best fit(BF), worst fit(WF), and next fit(NF) methods, had the disadvantage of waiting for a specific processor because they failed to allocate all processors arriving at the ready queue. The proposed algorithm in this paper is a simple block packing algorithm that allocates as many processors as possible to the largest block by sorting the size of the partitioned blocks(holes) and the size of the processor in the ready queue in descending order. The application of the proposed algorithm to nine benchmarking experimental data showed the performance of allocating all processors while having minimal internal fragment(IF) for all eight data except one data in which the weiting processor occurs due to partition errors.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.6B
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• pp.1183-1190
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• 1999

This paper presents an efficient hardware architecture to improve the frame memory interface occupying the largest hardware area together with motion estimator in implementing MPEG-2 video encoder as an ASIC chip. In this architecture, the memory size for internal data buffering and hardware area for frame memory interface control logic are reduced through the efficient memory map organization of the external SDRAM having dual bank and memory access timing optimization between the video encoder and external SDRAM. In this design, 0.5 m, CMOS, TLM (Triple Layer Metal) standard cells are used as design libraries and VHDL simulator and logic synthesis tools are used for hardware design add verification. The hardware emulator modeled by C-language is exploited for various test vector generation and functional verification. The architecture of the improved frame memory interface occupies about 58% less hardware area than the existing architecture[2-3], and it results in the total hardware area reduction up to 24.3%. Thus, the (act that the frame memory interface influences on the whole area of the video encoder severely is presented as a result.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.1
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• pp.175-182
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• 2011

In this paper, we implemented a high-performence memory controller which can accommodate processing blocks(multiple masters) in SoC for video signal processing. The memory controller is arbitrated by the internal arbiter which receives request signals from masters and sends grant and data signals to masters. The designed memory controller consists of Master Selector, Mster Arbiter, Memory Signal Generator, Command Decoder, and memory Signal Generator. It was designed using VHDL, and verified using the memory model of SAMSING Inc. For FPGA synthesis and verification, Quartus II of ATERA Inc. was used. The target device is Cyclone II. For simulation, ModelSim of Cadence Inc was used. Since the designed H/W can be stably operated in 174.28MHz, it satisfies the specification of SDRAM technology.