• 한국멀티미디어학회논문지
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• 제8권12호
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• pp.1658-1668
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• 2005

This paper presents the bytecode-to-SIL translator which enables the execution of the java program in EVM(Embedded Virtual Machine) environment without JVM(java Virtual Machine), translating bytecodes produced by compiling java programs into SIL(Standard Intermediate Language) codes. EVM, what we are now developing, is a virtual machine solution that can download and execute dynamic application programs written in sequential languages like C language as well as object oriented languages such as C#, Java, etc. EVM is a virtual machine mounted on embedded systems such as mobile device, set-top box, or digital TV, and converts the application program into SIL, an assembly language symbolic form, and execute it. SIL is a virtual machine code for embedded systems, based on the analysis of existing virtual machine codes such as bytecode, MSIL, etc. SIL has such features as to accommodate various programming languages, and in particularly has an operation code set to accept both object-oriented languages and sequential languages. After compiling, a program written in java language is converted to bytecode, and also executed by JVM platform but not in other platform such as .NET, EVM platform. For this reason, we designed and implemented the bytecode-to-SIL translator system for programs written in java language to be executed in the EVM platform without JVM. This work improves the execution speed of programs, enhances the productivity, and provides an environment for programmers to execute application programs at various platforms.

• 인터넷정보학회논문지
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• 제3권3호
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• pp.1-9
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• 2002

자바 언어의 실행 속도를 개선하기 위해 전통적인 컴파일 방법을 사용하여 바이트 코드를 특정 프로세서에서 수행될 수 있는 목적기계 코드로 변환하는 다양한 연구가 진행중이다. 패턴 매칭을 이용한 코드 생성 기법은 코드 확장 기법에 비해 양질의 코드를 생성할 수 있는 장점을 가지고 있다. 본 연구에서는 바이트 코드로부터 효과적으로 네이티브 코드를 생성하기 위해 레지스터 기반의 중간 언어를 효율적으로 생성할 수 있는 정형화된 패턴 기술 방법과 패턴 매칭 기법에 대해 제시한다. 또한 기술된 정형화 패턴을 활용하여 양질의 레지스터 기반 중간 코드를 생성하는 중간 코드 변환기를 설계하고 구현하였다.

• 전자공학회논문지B
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• 제32B권6호
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• pp.821-827
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• 1995

This paper presents a process control language for constructing multiloop control system. which include advanced control algorithms. In order to make controller, this language uses function blocks that do specific operations. Then, the total control algorithm is a set of function blocks, of which each block is represented as a function code. The function code is a line of simple ASCII codes denoting function, input, output, parameters. It is possible to use variables as input/output port of any block. Compared with other language using function block concept, the proposed one enables to use advanced control algorithms undefinitely, such as fuzzy, neural network, predictive controller, etc., because vector and matrix variables as input/output can be used freely in this language. To raise flexibility, we put an intermediate level, which is C-language code, between function code and target-dependent operation code.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 심포지엄 논문집 정보 및 제어부문
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• pp.187-189
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• 2007

In this paper, we present a model-driven approach for RTOS-based embedded software development and an automated tool that produces RTOS-specific code or RTOS-independent code. We define generic RTOS APIs (Application Programming Interface) that are not bound to any specific RTOS but provide most of typical RTOS services. Generic RTOS APIs can be used to describe application's RTOS-related behavior, The proposed API translator translates task code between C-code for specific RTOS and intermediate code using generic API. Also, the result can be extended to other RTOS's modifying XML transformation rule.

• 제어로봇시스템학회논문지
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• 제16권6호
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• pp.559-565
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• 2010

In this paper, we present a transformation method of source code from a POSIX (Portable Operating System Interface) based source code into an OSEK/VDX (Offene Systeme und deren Schnittstellen fur die Elektronik in Kraftfahrzeugen/Vehicle Distributed eXecutive) source code. As the electronic parts of automobile systems increase, the use of embedded software in automobile systems is also growing. Accordingly, many electronic systems are designed in automobile system with OSEK/VDX. Otherwise, one of the major problems of embedded software would be portability to other OS's. To enhance the portability and interoperability of embedded software, we propose a source code transformation method from POSIX to OSEK/VDX based on API (Application Programming Interface) translation method. Considering the characteristics of the OSEK/VDX which uses OIL (OSEK/VDX Implementation Language) standard, transformation process is performed with source code transformation and OIL code generation. For the validity of the proposed method, the transformation experiment is given using Micro-C OS II and OSEK/VDX with XC167CI micro-controller.

• 한국압력기기공학회 논문집
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• 제12권1호
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• pp.107-114
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• 2016

Four cylindrically shaped IHXs(Intermediate Heat Exchangers) are installed in the PHTS(Primary Heat Transfer System) of the PGSFR(Prototype Gen IV Sodium cooled Fast Reactor). As for the IHX, the temperature difference of structure is inevitable result caused by heat transfer between primary coolant sodium and IHTS(Intermediate Heat Transport System) sodium. It is necessary to evaluate the high temperature structural integrity of IHXs which operate at the elevated temperature condition over the creep temperature. In this paper, the high temperature structural integrity of IHX under assumed loading conditions has been reviewed according to ASME code.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.97-100
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• 2002

A procedural interface libary for IEEE Verilog 1364-2001 is developed. The lexer and scanner are developed to handle “Verilog-2001” which is the first major update to the Verilog language since its inception in 1984. Also the newly developed XML intermediate format for Verilog-2001 is Presented in the paper. By using the XML intermediate, it allows the portable and scalable development of various kinds of applications. The XML DTD(Document Type Definition) of Verilog is defined and the corresponding XML intermediate format is developed. The paper describes example application of code rule checker which is built using the language interface library.

• 디지털산업정보학회논문지
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• 제7권2호
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• pp.29-37
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• 2011

Java bytecode verification is a critical process to guarantee the safety of transmitted Java applet on the web or contemporary embedded devices. We propose a design of framework which enables to analyze and verify java bytecode. The designed framework translates from a java bytecode into the intermediate representation which can specify a properties of program without using an operand stack. Using the framework is able to produce automatically error specifications that could be occurred in a program and express specifications annotated in intermediate representation by a user. Furthermore we design a verification condition generator which converts from an intermediate representation to a verification condition, a verification engine which verifies verification conditions from verification condition generator, and a result reporter which displays results of verification.

• ETRI Journal
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• 제46권3호
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• 융합신호처리학회논문지
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• 제8권4호
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• pp.272-278
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• 2007

본 논문에서는 모델 기반 접근 방법을 이용하여 임베디드 소프트웨어를 개발하기 위한 자동화된 API 변환기에 대하여 기술한다. MDA(Model Driven Architecture)가 임베디드 소프트웨어의 개발에 관해서는 지원이 매우 미약하기 때문에, 우리는 MDA의 장점인 구현 공정의 자동화를 포함하면서도 실시간 오버헤드 문제를 해결할 수 있는 새로운 접근 방법을 제시한다. 첫 번째로, 어느 특정 RTOS에 의존하지 않지만 전형적인 RTOS 서비스들의 대부분을 제공할 수 있도록 Generic API를 정의한다. 우리는 이 Generic API를 이용하여 타겟 응용프로그램의 RTOS와 관련된 행동을 CIC(Common Intermediate Code)에서 표현할 수 있다. 그 다음에, Generic API를 이용하여 기술된 CIC를 특정 RTOS에서 수행할 수 있는 C-코드로 변환할 수 있는 변환 툴을 제안한다. 제안된 API 변환기는 외부에 정의되어 있는 XML 변환 규칙을 이용하여 코드를 변환한다. 따라서 API 변환기는 이 변환 규칙을 수정하거나 추가하여 다른 RTOS로 적용할 수 있도록 확장이 가능하다. 실험을 통하여 제안된 방법을 확인한다.