• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권1호
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• pp.34-39
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• 2014

This paper discusses the 3-level charge pumping (CP) method in planar-type Silicon-Oxide-High-k-Oxide-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason of the degradation of data retention properties. In the CP technique, pulses are applied to the gate of the MOSFET which alternately fill the traps with electrons and holes, thereby causing a recombination current Icp to flow in the substrate. The 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.59-64
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• 1994

The Si-SiO$_2$interface trpas of the degraded short-channel SONOSFET memory devices were investigated using the charge pumping techniques. The degradation of devices with write/erase cycle appeared as the increase of the Si-SiO$_2$interface trap density. In order to determine the capture cross-section of the interface trap. I$\_$CP/-V$\_$GL/ characteristic curves were measured at different temperatures. Also, the spatial distributions of Si-SiO$_2$interface trap were examined by the variable-reverse bias boltage method.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2018년도 추계학술대회
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• pp.514-516
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• 2018

이 논문은 모놀리식 3차원 공정 시 열에 의해 생성될 수 있는 계면 포획 전하가 3차원 인버터의 특성에 미치는 영향에 대하여 TCAD 시뮬레이션을 통해 확인하였다. 계면 포획 전하는 문턱 전압 및 ILD 두께에 따른 문턱 전압의 변화량에도 영향을 주었고 3차원 인버터의 입출력 특성에도 영향을 주는 것을 확인하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.453-456
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• 1999

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor)NVSM(nonvolatile semiconductor memory) cell were investigated by single charge pumping method. The used device was fabricated by 0.35 7m standard logic fabrication including the ONO cell process. This ONO dielectric thickness is tunnel oxide 24 $\AA$, nitride 74 $\AA$, blocking oxide 25 $\AA$, respectively. Keeping the pulse base level in accumulation and pulsing the surface into inversion with increasing amplitudes, the charge pumping current flow from the single junction. Using the obtained I$_{cp}$-V$_{h}$ curve, the local V$_{t}$ distribution, doping concentration, lateral interface trap distribution and lateral memory trap distribution were extracted. The maximum N$_{it}$($\chi$) of 1.62$\times$10$^{19}$ /cm$^2$were determined.mined.d.

• ETRI Journal
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• 제15권2호
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• pp.11-25
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• 1993

Interface trap densities at gate oxide/silicon substrate ($SiO_2/Si$) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.

• 한국정보통신학회논문지
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• 제19권12호
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• pp.2899-2904
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• 2015

3차원 순차적 집적회로에서 열에 의한 손상으로 생성되는 계면 포획 전하가 트랜지스터의 드레인 전류-게이트 전압 특성에 미치는 영향을 소개한다. 2차원 소자 시뮬레이터를 이용해서 산화막 층에 계면 포획 전자 분포를 추출한 결과를 설명한다. 이 계면 포획 전자분포를 고려한 3차원 순차적 집적회로에서 Inter Layer Dielectric (ILD)의 길이에 따른 하층 트랜지스터의 게이트 전압의 변화에 따라서 상층 트랜지스터의 문턱전압 $V_{th}$의 변화량에 대해서 소개한다. 상대적으로 더 늦은 공정인 상층 $HfO_2$층 보다 하층 $HfO_2$층과 양쪽 $SiO_2$층이 열에 의한 영향을 더 많이 받았다. 계면 포획 전하 밀도 분포를 사용하지 않았을 때 보다 사용 했을 때 $V_{th}$ 변화량이 더 적게 변하는 것을 확인 했다. 3차원 순차적 인버터에서 ILD의 길이가 50nm이하로 짧아질수록 점점 더 $V_{th}$ 변화량이 급격히 증가하였다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• 반도체디스플레이기술학회지
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• 제18권4호
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• pp.134-137
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• 2019

In this paper, the data retention characteristics were analyzed to find out the thickness effect on the trap energy distribution of silicon nitride in the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices. The nitride films were prepared by low pressure chemical vapor deposition (LPCVD). The flat band voltage shift in the programmed device was measured at the elevated temperatures to observe the thermal excitation of electrons from the nitride traps in the retention mode. The trap energy distribution was extracted using the charge decay rates and the experimental results show that the portion of the shallow interface trap in the total nitride trap amount including interface and bulk trap increases as the nitride thickness decreases.

• 한국전기전자재료학회논문지
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• 제13권10호
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• pp.822-827
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• 2000

The Si-SiO$_2$interface trap and nitride bulk trap distribution of SONOSFET(polysilicon-oxide-nitride-oxide-semiconductor field effect transistor) NVSM (nonvolatile semiconductor memory) cell is investigated by single junction charge pumping method. The device was fabricated by 0.35㎛ standard logic fabrication process including the ONO stack dielectrics. The thickness of ONO dielectricis are 24$\AA$ for tunnel oxide, 74 $\AA$ for nitride and 25 $\AA$ for blocking oxide, respectively. By the use of single junction charge pumping method, the lateral profiles of both interface and memory traps can be calculated directly from experimental charge pumping results without complex numerical simulation. The interface traps were almost uniformly distributed over the whole channel region and its maximum value was 7.97$\times$10$\^$10/㎠. The memory traps were uniformly distributed in the nitride layer and its maximum value was 1.04$\times$10$\^$19/㎤. The degradation characteristics of SONOSFET with write/erase cycling also were investigated.