• ETRI Journal
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• 제30권5호
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• pp.644-652
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• 2008

In this paper, a low-power CMOS interface circuit is designed and demonstrated for capacitive sensor applications, which is implemented using a standard 0.35-${\mu}m$ CMOS logic technology. To achieve low-power performance, the low-voltage capacitance-to-pulse-width converter based on a self-reset operation at a supply voltage of 1.5 V is designed and incorporated into a new interface circuit. Moreover, the external pulse signal for the reset operation is made unnecessary by the employment of the self-reset operation. At a low supply voltage of 1.5 V, the new circuit requires a total power consumption of 0.47 mW with ultra-low power dissipation of 157 ${\mu}W$ of the interface-circuit core. These results demonstrate that the new interface circuit with self-reset operation successfully reduces power consumption. In addition, a prototype wireless sensor-module with the proposed circuit is successfully implemented for practical applications. Consequently, the new CMOS interface circuit can be used for the sensor applications in ubiquitous sensor networks, where low-power performance is essential.

• ETRI Journal
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• 제46권5호
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• pp.878-889
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• 2024

To expand the scale of spiking neural networks (SNNs), an interface circuit that supports multiple SNN cores is essential. This circuit should be designed using an asynchronous approach to leverage characteristics of SNNs similar to those of the human brain. However, the absence of a global clock presents timing issues during implementation. Hence, we propose an intermediate latching template to establish asynchronous nonlinear connectivity with multipipeline processing between multiple SNN cores. We design arbitration and distribution blocks in the interface circuit based on the proposed template and fabricate an interface circuit that supports four SNN cores using a full-custom approach in a 28-nm CMOS (complementary metal-oxide-semiconductor) FDSOI (fully depleted silicon on insulator) process. The proposed template can enhance throughput in the interface circuit by up to 53% compared with the conventional asynchronous template. The interface circuit transmits spikes while consuming 1.7 and 3.7 pJ of power, supporting 606 and 59 Mevent/s in intrachip and interchip communications, respectively.

• 전기의세계
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• 제26권6호
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• pp.41-47
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• 1977

The paper deals with the fundamental specification for the physical implementation of interface circuit, which will play an important role in information and signal trammission between computer and controlled system, and also we have proved that the digital contoller will be able to improve the data handling of interface circuit.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 하계종합학술대회 논문집
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• pp.749-752
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• 1999

A new interface circuit for variable resistive sensors is proposed. The interface circuit compose of only two strain gages, a voltage-to-current converter, and current mirror with two outputs. A new dual slope A/D converter based on linear operational transconductance amplifier for the testing of prototype interface circuit is also described. The theory of operation is presented and experimental results are used to verify the theoretical predictions. The results show close agreement between predicted behaviour and experimental performance.

• 전기학회논문지
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• 제56권6호
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• pp.1087-1091
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• 2007

Exact impedance modeling of the electrode/electrolyte interface is important in bio-signal sensing electrode development. Therefore, the investigation of the equivalent circuit models for the interface has been pursued for a long time by several researchers. Previous circuit models fit the experimental results in limited conditions such as frequency range, type of electrode, or electrolyte. This paper describes a new electrical circuit model and its capability of fitting the experimental results. The proposed model consists of three resistors and two constant phase elements. Electrochemical impedance spectroscopy was used to characterize the interface for Au, Pt, and stainless steel electrode in 0.9% NaCl solution. Both the proposed model and the previous model were applied to fit the measured impedance results for comparison. The proposed model fits the experimental data more accurately than other models especially at the low frequency range, and it enables us to predict the impedance at very low frequency range, including DC, using the proposed model.

• ETRI Journal
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• 제29권1호
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• pp.70-78
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• 2007

A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow low-voltage circuit operation. A simple 1-bit first-order delta-sigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0.35 ${\mu}m$ CMOS technology and draws less than 200 ${\mu}A$ from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% non-linearity error.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 추계학술대회 논문집 학회본부
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• pp.419-421
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• 1996

We propose the digitized pressure sensor and the interface circuit to read directly the pressure signal in the digital form. The interface circuit has the control clock, comparator, and bit value decision circuit. The digitized sensor and interface circuit are integrated on the one chip using the post processing after IC fabrication. The dimension of the fabricated digitized pressure sensor is $3{\times}6{\times}1mm^3$.

• 정보처리학회논문지A
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• 제9A권1호
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• pp.53-60
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• 2002

본 논문에서는 USB(Universal Serial Bus) 인터페이스를 이용하여 Gray Mode Graphic STN LCD를 구동하는 구동회로를 제안한다. 제안된 구동회로는 사용자가 PC상에서 작업한 이미지 데이터를 USB 인터페이스를 이용하여 LCD로 전송할 수가 있다. 따라서 기존의 방식과는 달리 마이크로프로세서를 사용하지 않기 때문에 사용자가 손쉽게 LCD를 구동할 수 있는 장점이 있다. 제안한 LCD 구동회로 부분은 VHDL(VHSIC Hardware Description Language)로 설계하여 시뮬레이션을 수행하고 ALTERA사의 EPF10K10TC144-3 FPGA를 사용하여 구현하였다. USB 인터페이스 부분은 MS-Visual C++ 6.0으로 프로그래밍하였다. 한편, 제안한 구동회로를 테스트 보드를 구성한 후에 하드웨어 동작 검증을 수행하여 그 효용성을 입증하였다. 본 논문에서 제안한 구동회로를 현재 시판중인 마이크로프로세서를 사용하는 타 업체의 구동회로와 비교한 결과는 구동회로의 작동 편이성, 제작시 소요되는 비용 등에서 우수함을 나타내었다.

• 한국정보통신학회논문지
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• 제25권8호
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• pp.1130-1133
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• 2021

In this paper, a miniaturized sensor interface circuit for the respiration detection system is proposed. Respiratory diagnosis is one of the main ways to predict various diseases. The proposed system consists of respiration detection sensor, temperature sensor, and interface circuits. Electrochemical type gas sensor using solid electrolytes is adopted for respiration detection. Proposed system performs sensing, amplification, analog-to-digital conversion, digital signal processing, and i2c communication. And also proposed system has a small form factor and low-cost characteristics through optimization and miniaturization of the circuit structure. Moreover, technique for sensor degradation compensation is introduced to obtain high accuracy. The size of proposed system is about 1.36 cm².

• 한국전자통신학회논문지
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• 제14권3호
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• pp.529-536
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• 2019

스마트 센서 시스템에 압전 에너지 하베스터를 적용하기 위해서는 AC-DC 정류기를 비롯한 에너지 하베스트 인터페이스 회로가 필수적이다. 본 논문에서는 기본적인 회로인 Full Bridge Rectifier(: FBR) 회로와 동기식 압전 에너지 하베스트 인터페이스 회로의 성능을 보드레벨 시뮬레이션으로 비교하였다. 그 결과, 동기식 압전 에너지 하베스트 인터페이스 회로 중 하나인 Synchronous Electric Charge Extraction(: SECE) 회로가 FBR에 비해 출력 전력이 약 4 배 이상 더 컸고, 부하 변동에도 변화가 거의 없었다. 그리고, 출력 전압이 40V 이상인 압전 에너지 하베스터용 SECE 회로에 필수적인 고전압 비교기를 0.35 um BCD 공정으로 설계하였다. 설계한 고전압 비교기를 적용한 SECE 회로는 출력 전력이 FBR 회로 보다 427 % 향상됨을 검증하였다.