• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.6 s.360
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• pp.83-88
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• 2007

In this paper, we propose the function verification method of the OLED(Organic Light Emitting Diode) drive IC using PLI verification method. This method uses the HDL(Hardware Description Language) simulator, PLI(Programing Language Interface), and GUI (Graphic User Interface) image viewer. This method improves the execute efficiency 40 times than conventional function verification methods. The proposed method can be used efficiently for function verification of DDI(display driver IC) design step.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.2
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• pp.259-266
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• 2021

USB bus not only works with convenience but also transmits data fast and becomes a standard peripheral interface between FPGA development board and personal computer. In this paper FPGA verification system with slave FIFO interface for Cypress FX3 USB 3 bridge chip was implemented. The designed slave FIFO interface consists of host interface module based on FIFO structure, master bus controller and command decoder and supports streaming communication interface for FX3 bridge chip and memory-mapped input and output interface for user design circuit. The ZestSC3 board with Cypress FX3 USB 3 bridge chip and Xilinx Artix FPGA(XC7A35T-1C5G3241) was used to implement FPGA verification system. It was verified that the FPGA verification system for user design circuit operated correctly under various clock frequencies using GUI software developed by visual C# and C++ DLL. The designed slave FIFO interface for FPGA verification system has modular structure and can be applicable to the different user designs with memory-mapped I/O interface.

• Journal of KIISE:Software and Applications
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• v.37 no.4
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• pp.323-339
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• 2010

The complexity of embedded systems and the effort to develop them has been rising in proportion with their importance. Also, the heterogeneity of the hardware and software parts in embedded systems makes it more challenging to develop. Errors caused by hardware/software interfaces, especially, account for up to 13 percent of failures with an increasing trend. Therefore, verifying the interface between hardware and software in embedded system is one of the most important research areas. However, current approaches such as co-simulation method and model checking have explicit limitations. In this paper, we propose the synthesizable interface co-verification framework for hardware/software co-design. Firstly, we introduce the separate interface specifications for the heterogeneous components to describe hardware design and software design. Our specifications are expressive enough to describe both. We also provide the transformation rules from the software specification to the hardware specification so that the whole system can be described from the software view. Secondly, we address the solution of verifying the interface of the software and hardware design by adopting and extending existing verification-techniques and extending them. In hardware interface verification, we exploit the model checking technique and provide more efficient verification by closing the hardware design from the assumption of the software behavior which is ensured by software verification step. Lastly, we generate the interface codes such as device APIs, device driver, and device controller from the specification so that verified hardware and software codes can be synthesized without extra efforts.

• International Journal of Fuzzy Logic and Intelligent Systems
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• v.4 no.3
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• pp.271-276
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• 2004

This paper is a research on the dynamic signature verification of error rate which are false rejection rate and false acceptance rate, the size of signature verification engine, the size of the characteristic vectors of a signature, the ability to distinguish similar signatures, the processing speed and so on. Also, we present our efficient user interface and performance results.

• Journal of the Korean Society for Railway
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• v.7 no.2
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• pp.114-119
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• 2004

According to the computerization of railway signalling systems. the communication protocol for interface between these systems are required. Therefore the new communication protocol for railway signaling system is required. Generally, there are two verification method for new designed protocol in the industrial and academic fields. One is the laboratory testing method which is very popular and general technique. In our research the comparison between existing and new designed protocol for signaling is described and the verification test results are also represented. From these laboratory test, we are verified the conformance of new designed protocol. Another method is verified by formal method. The format verification method is widely used at safety-critical system design but this approach is nor popular at verification communication protocol. However it is very important to verify the safety of new designed protocol for railway signaling system because signaling systems are very safety-critical systems. So, the methodology for formal verification of designed protocol is also reviews in this paper.

• Journal of Aerospace System Engineering
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• v.13 no.3
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• pp.40-47
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• 2019

This paper proposes the environment construction and test method of system integration laboratory (SIL) and system integration test (SIT) for verification of interface between onboard equipment and ground control equipment of unmanned aerial systems (UAS). This research also describes the interface environment between subsystems built in SIL and verification methods for the systems' operation logic through simulated flights. Similarly, the paper handles the ground integration test process of UAS in the real testing environments.

• Proceedings of the IEEK Conference
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• 2002.06a
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• pp.291-294
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• 2002

This paper proposed interface test method for performance verification of communication and broadcasting satellite between communication and broadcasting satellite payload and EGSE(Electrical Ground Support Equipment). We need ground support equipment for test them to performance verification and conform interface function of payload. This paper define tile telemetry transfer method for control payload using GSE(Ground Support Equipment) and receive telemetry data collected from GSE through bus simulator

• Proceedings of the CALSEC Conference
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• 2005.03a
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• pp.299-304
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• 2005

This paper is a research on the dynamic signature verification of error rate which are false rejection rate and false acceptance rate, the size of signature verification engine, the size of the characteristic vectors of a signature, the ability to distinguish similar signatures, and so on. We suggest feature extraction and comparison method of the signature verification. Also, we have implemented our system with Java technology for more efficient user interfaces and various OS Platforms.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.7
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• pp.115-122
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• 1995

This paper presents the simulation environment that verifies whether a new microprocessor described with HDL is compatible with MS-DOS. The phrase 'compatible with MS-DOS' means that the microprocessor can execute MS-DOS without any modification of MS-DOS's binary code. The proposed verification environment consists of HDL simulator and user interface module. And the communications between them are performed by using sockets which UNIXprovide. The HDL simulator is equipped with several functions, which use PLI to emulate ROM-BIOS facilities. The ROM-BIOS emulation routine is described by using these functions. User interface module utilizes S/MOTIF and participates in emulating PC monitor and keyboard. The verification environment is tested by executing the MS-DOS commands (DIR, FORMAT, DATE, TIME etc.) with the HDL model of microprocessor, and the display of user interface module verifies that the environment works correctly. In this paper, the method of constructing the verification environment is presented, and the simulation results are summarized.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.4
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• pp.890-895
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• 2005

Dynamic (On-line) signature verification system consists of preprocessing, feature extraction, comparison and decision process for internal processing, and registration and verification windows for the user interface. We describe an implementation and design for an advanced dynamic signature verification system. Also, we suggest the method of feature extraction, matching algorithm, efficient user interface and an objective criteria for evaluating the performance.