• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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• pp.116-119
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• 1994

The characteristics of the Si-SiO$_2$ interface and the degradation in the short channel(L${\times}$W=1.7$\mu\textrm{m}$${\times}$15$\mu\textrm{m}$) SONOSFET nonvolatile memory devices, fabricated on the basis of the existing n-well CMOS processing technology for 1 Mbit DRAM with the 1.2$\mu\textrm{m}$ m design rule, were investigated using the charge pumping method. The SONOSFET memories have the tripple insulated-gate consisting of 30${\AA}$ tunneling oxide 205${\AA}$ nitride and 65${\AA}$ blocking oxide, The acceleration method which square voltage pulses of t$\_$p/=10msec, Vw=+19V and V$\_$E/=-22V continue to be alternatly applied to gale, was used to investigate the degradation of SONOSFET memories with the write/erase cycle. The degradation characteristics were ascertained by observing the change in the energy and spatial distributions of the interface trap density.

• 한국전기전자재료학회논문지
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• 제20권7호
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• pp.569-574
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• 2007

In this paper, the reliability (NBTI degradation: ${\Delta}V_{th}$) and device characteristic of nano-scale PMOSFET with plasma nitrided oxide (PNO) is characterized in depth by comparing those with thermally nitrided oxide (TNO). PNO case shows the reduction of gate leakage current and interface state density compared to TNO with no change of the $I_{D.sat}\;vs.\;I_{OFF}$ characteristics. Gate oxide capacitance (Cox) of PNO is larger than TNO and it increases as the N concentration increases in PNO. PNO also shows the improvement of NBTI characteristics because the nitrogen peak layer is located near the $Poly/SiO_2$ interface. However, if the nitrogen concentration in PNO oxide increases, threshold voltage degradation $({\Delta}V_{th})$ becomes more degraded by NBT stress due to the enhanced generation of the fixed oxide charges.

• 한국전기전자재료학회논문지
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• 제25권7호
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• pp.521-524
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• 2012

We report on variations of electrical properties with different active layer thickness and post-annealing temperature in amorphous In-Ga-Zn-O (IGZO) thin-film transistors (TFTs). In particular, subthreshold swing (SS) of the IGZO-TFTs was improved as increasing the active layer thickness at an given post-annealing temperature, accompanying the negative shift in turn-off voltage. However, as increasing post-annealing temperature, only turn-off voltage was shifted negatively with almost constant SS value. The effect of the active layer thickness and post-annealing temperature on electrical properties, such as SS, field effect mobility and turn-off voltage in IGZO-TFTs has been explained in terms of the variation of trap density in IGZO channel layer and at gate dielectric/IGZO interface.

• 한국응용과학기술학회지
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• 제30권2호
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• pp.290-296
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• 2013

We analysed interfacial traps in organic thin-film transistors (TFTs) in which pentacene and 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) organic semiconductors were deposited by means of vacuum-thermal evaporation and drop-coating methods, respectively. The thermally-deposited pentacene film consists of dentritic grains with the average grain size of around 1 m, while plate-like crystals over a few hundred microns are observed in the solution-processed TIPS-pentacene film. From the transfer characteristics of both TFTs, lower subthreshold slope of 1.02 V/decade was obtained in the TIPS-pentacene TFT, compared to that (2.63 V/decade) of the pentacene transistor. The interfacial trap density values calculated from the subthreshold slope are about $3.4{\times}10^{12}/cm^2$ and $9.4{\times}10^{12}/cm^2$ for the TIPS-pentacene and pentacene TFTs, respectively. Herein, lower subthreshold slope and less interfacial traps in TIPS-pentacene TFTs are attributed to less domain boundaries in the solution-processed TIPS-pentacene film.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.287-287
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• 2011

ITRS(international technology roadmap for semiconductors)에 따르면 MOS (metal-oxide-semiconductor)의 CD(critical dimension)가 45 nm node이하로 줄어들면서 poly-Si/SiO2를 대체할 수 있는 poly-Si/metal gate/high-k dielectric이 대두되고 있다. 일반적으로 metal gate를 식각시 정확한 CD를 형성시키기 위해서 plasma를 이용한 RIE(reactive ion etching)를 사용하고 있지만 PIDs(plasma induced damages)의 하나인 PICD(plasma induced charging damage)의 발생이 문제가 되고 있다. PICD의 원인으로 plasma의 non-uniform으로 locally imbalanced한 ion과 electron이 PICC(plasma induced charging current)를 gate oxide에 발생시켜 gate oxide의 interface에 trap을 형성시키므로 그 결과 소자 특성 저하가 보고되고 있다. 그러므로 본 연구에서는 이에 차세대 MOS의 metal gate의 식각공정에 HDP(high density plasma)의 ICP(inductively coupled plasma) source를 이용한 중성빔 시스템을 사용하여 PICD를 줄일 수 있는 새로운 식각 공정에 대한 연구를 하였다. 식각공정조건으로 gas는 HBr 12 sccm (80%)와 Cl2 3 sccm (20%)와 power는 300 w를 사용하였고 200 eV의 에너지로 식각공정시 TEM(transmission electron microscopy)으로 TiN의 anisotropic한 형상을 볼 수 있었고 100 eV 이하의 에너지로 식각공정시 하부층인 HfO2와 높은 etch selectivity로 etch stop을 시킬 수 있었다. 실제 공정을 MOS의 metal gate에 적용시켜 metal gate/high-k dielectric CMOSFETs의 NCSU(North Carolina State University) CVC model로 effective electric field electron mobility를 구한 결과 electorn mobility의 증가를 볼 수 있었고 또한 mos parameter인 transconductance (Gm)의 증가를 볼 수 있었다. 그 원인으로 CP(Charge pumping) 1MHz로 gate oxide의 inteface의 분석 결과 이러한 결과가 gate oxide의 interface trap양의 감소로 개선으로 기인함을 확인할 수 있었다.

• 접착 및 계면
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• 제21권3호
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• pp.86-92
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• 2020

본 연구에서 소스/드레인 전극이 위치하는 기판의 접촉영역과 두 전극사이 채널영역의 표면 에너지를 선택적으로 다르게 제어하여 고분자 트랜지스터의 소자성능과 전하주입 특성에 미치는 영향을 확인하였다. 채널영역의 표면에너지를 낮게 유지하면서 접촉영역의 표면에너지를 높였을 때 고분자 트랜지스터의 전하이동도는 0.063 ㎠/V·s, 접촉저항은 132.2 kΩ·cm, 그리고 문턱전압이하 스윙은 0.6 V/dec로 나타났으며, 이는 원래 소자에 비해 각각 2배와 30배 이상 개선된 결과이다. 채널길이에 따른 계면 트랩밀도를 분석한 결과, 접촉영역에서 선택적 표면처리에 의해 고분자반도체 분자의 공액중첩 방향과 전하주입 방향이 일치되면서 전하트랩 밀도가 감소한 것이 성능향상의 주요한 원인으로 확인되었다. 본 연구에서 적용한 전극과 고분자 반도체의 접촉영역에 선택적 표면처리 방법은 기존의 계면저항을 낮추는 다양한 공정과 함께 활용됨으로써 트랜지스터 성능향상을 최대화할 수 있는 가능성을 가진다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.664-674
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• 2016

The electrical properties of Ti/p-type InP Schottky diodes with and without polyaniline (PANI) interlayer was investigated using current-voltage (I-V) and capacitance-voltage (C-V) measurements. The barrier height of Ti/p-type InP Schottky diode with PANI interlayer was higher than that of the conventional Ti/p-type InP Schottky diode, implying that the organic interlayer influenced the space-charge region of the Ti/p-type InP Schottky junction. At higher voltages, the current transport was dominated by the trap free space-charge-limited current and trap-filled space-charge-limited current in Ti/p-type InP Schottky diode without and with PANI interlayer, respectively. The domination of trap filled space-charge-limited current in Ti/p-type InP Schottky diode with PANI interlayer could be associated with the traps originated from structural defects prevailing in organic PANI interlayer.

• E2M - 전기 전자와 첨단 소재
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• 제8권2호
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• pp.171-175
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• 1995

Optimum condition of remote plasma enhanced chemical vapor deposition using orthogonal array method was chosen. Characteristics of oxide films deposited by RPECVD with SiH$_{4}$ and N$_{2}$O gases were investigated. Etching rate of the optimized SiO$_{2}$ films in P-etchant was about 6[A/s] that was almost the same as that the high temperature thermal oxide. The films showed high dielectric breakdown field of more than 7[MV/cm] and a resistivity of 8*10$^{13}$ [.ohmcm] around at 7[MV/cm]. The interface trap density of SiO$_{2}$/Si interface around the midgap derived from the high frequency C-V curve was about 5*10$^{10}$ [/cm$^{2}$eV]. It was observed that the dielectric constant of the optimized SiO$_{2}$ film was 4.29.

• 한국전기전자재료학회논문지
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• 제16권12S호
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• pp.1242-1247
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• 2003

In order to passivate the GaAs surface, silicon-nitride films were fabricated by using laser CVD method. SiH$_4$ and NH$_3$ were used to obtain SiN films in the range of 100∼300$^{\circ}C$ on p-type (100) GaAs substrate. To determine interface characteristics of the metal-insulator-GaAs structure, electrical measurements were performed such as C-V curves and deep level transient spectroscopy (DLTS). The results show that the hysteresis was reduced and interface trap density was lowered to 1,012 ∼ 1,013 at 100 ∼ 200$^{\circ}C$. According to the study of surface leakage current, the passivated CaAs has less leakage current compared to non-passivated substrate.

• E2M - 전기 전자와 첨단 소재
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• 제9권1호
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• pp.9-17
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• 1996

Plasma enhanced chemical vapor deposition (PECVD) allows low temperature processing and so it is widely used, but it causes instability of devices due to serious amount of impurities within the film. In this paper, electrical and chemical characteristics of the PECVD oxynitride film formed by different N$_{2}$O to N$_{2}$O+NH$_{3}$ gas ratio is studied. It has been found that hydrogen concentration of PECVD oxynitride film was decreased from 4.25*10$^{22}$ [cm$^{-2}$ ] to 1.18*10$^{21}$ [cm$^{-2}$ ] according to the increase of N$_{2}$O gas. It was also found that PECVD oxynitride films have low trap density in the oxide and interface in comparison with PECVD nitroxide films, and has higher refractive index and capacitance than oxide films. In particular, oxynitride film formed in gas ratio of N$_{2}$O/(N$_{2}$O+NH$_{3}$)= 0.88 shows increased capacitance and decreased leakage current due to small portion of hydrogen in oxide and the accumulation of nitrogen about 4[atm.%] at the interface.