• The Journal of Information Technology
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• v.3 no.1
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• pp.117-124
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• 2000

This paper proposes a new heuristic algorithm of a low power hardware allocation for Design Automation. The proposed algorithm works on scheduled input graph and allocates functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. The low power factor of the capacitance is reduced during the allocation. As the resource number reduce maximal . This paper shows the effectiveness of the algorithm by comparing experiments of existing system of the non low power.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.2
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• pp.1-9
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• 1997

For the reduction of parasitic inductance and matching of bonding wire in the package of microwave devices, we propose multiple bonding wires buried in a dielectric material of FR-4 composite. This structure is analyzed using the method of moments (MoM) and compared with the common bondwires and ribbon interconnections. The FR-4 composite is modelled by the cole-cole model which can consider the loss and the variation of the permittivity in a frequency. At 20 GHz, the parasitic reactance is reduced by 90%, 80%, 60% compared to those of a single bonding wire in air, double bonding wires in air and ribbon interconnection in air, respectively. Also, the new bondwire shows very good matching of 60.ohm characteristic impedance and has 15dB, 10dB, 5dB improvement of the return loss and 2.5dB, 0.7dB, 0.2dB improvement of the insertion loss compared to the common interconnections. This technique can minimize the parasitic effect of bondwires in microwave device packaging.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.728-734
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• 2001

Delay defects on I/O pads, interconnections of a board, or interconnections among embedded cores can not be tested with the current IEEE 1149.1 boundary scan design. This paper introduces a simple design technique which slightly modifies the TAP controller to test delay defects at system speed. Experimental design shows that the technique proposed requires much less area than a commercial approach.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.375-378
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• 2001

A 640Gb/s very advanced ATM switching system using 0.25um CMOS VLSI, 40 layer ceramic MCM and 10Gb/s, 8 wavelength 8$\times$8 optical WDM interconnection has been fabricated. To break though the interconnection bottleneck, optical WDM interconnection is used. It has 20Gb/s 8 wavelength 8$\times$8 interconnection capability. It realizes 640Gb/s interconnections within a very small size. Preliminary tests show that 800b1s ATM switch MCM and optical WDM interconnection technologies can be applied to future high speed broadband networks

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.11 no.3
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• pp.365-371
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• 2000

In this paper, we introduce a noise reduction method using polarizers in a wireless optical interconnections. If we use polarizers in a differential detector, the noise reduction capability is improved. In a case that two optical signal beams of similar wavelength are overlapped in space and crosstalk is a serious problems, we can detect each channel separately without crosstalk using two orthogonal polarizers. This method is very simple and easy to use.

• Proceedings of the KSME Conference
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• 2008.11a
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• pp.1265-1270
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• 2008

Electromigration is a one of a critical failure mechanism in microelectronic devices. Minimizing the thin film interconnections in microelectronic devices make high current densities at electrrical line. Under high current densities, an electromigration becomes critical problems in a microelectronic device. This phenomena under DC conditions was investigated with high temperature. The current density of 1.5MA/cm2 was stressed in interconnections under DC condition, and temperature condition $150^{\circ}C,\;175^{\circ}C,\;200^{\circ}C$. By increasing of thin film interconections, microelectronic devices durability is decreased and it gets more restriction by temperature. Electromigration makes electronic open by void induced, and hillock induced makes electronic short state.

• The Transactions of the Korea Information Processing Society
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• v.7 no.4
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• pp.1255-1262
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• 2000

This paper proposes a hardware allocation and binding algorithm for ASIC Design. The proposed algorithm works on schedules input graph and simultaneously allocates and binds functional units, interconnections and registers by considering interdependency between operations and storage elements in each control step, in order to share registers and interconnections connected to functional units, as much as possible. Especially, he register allocation is executes the allocation optimal using graph coloring. This paper shows the effectiveness of the algorithm by comparing experiments to determine number of functional unit and register in advance or to separate executing allocation and binding of existing system.

• International Journal of Automotive Technology
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• v.3 no.2
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• pp.79-88
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• 2002

Emergent Collision Avoidance Systems (CAS's) are beginning to assist drivers by performing specific tasks and extending the limits of driver's perception. As CAS's evolve from simple systems handling discrete tasks to complex systems managing interrelated driving tasks, the risk of failure from hidden causes greatly increases. The successful implementation of such a complex system depends upon a robust software architecture. Host of the difficulty in implementing system arises from interconnections between the components. The CAS architecture presented in this paper focuses on these interconnections to mitigate this problem. Moreover, by constructing the GAS architecture through the composition of existing architectural styles, the resulting system will exhibit predictable qualities. Some of the qualities represent limitations that translate into constraints on the system. Others are beneficial aspects that satisfy stakeholder requirements .

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.2
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• pp.102-108
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• 1988

In this paper, a channel routing algorithm which considers cycle problem is proposed. The requirements of routing is given by pin numbers which imply interconnections between a upper block and lower block of the channel. Output is represented by interconnections among equipotential pins. When input is given, the algorithm constructs a channel representation graph and makes weight of each net. And then it checks cycle and finidhes the routing. If the cycle is detected, it finds path with maze routing. This algorithm have coded in C language on IBM-PC /AT. If cycle is not detected, the results are near optimal values. If it is detected, routing is possible as well.

• Journal of the Optical Society of Korea
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• v.1 no.1
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• pp.52-59
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• 1997

In this paper, we propose a system design for a parallel3-dimensional optical interconnection network utilizing variable grating mode liquid crystal devices (VGM LCD's) which are optical transducers capable of performing intensity-to-spatial-frequency conversion. The proposed system performs real-time, reconfigurable, but blocking and nonbroadcasting 3-dimensional optical interconnections. The operating principles of the 3-D optical interconnection network are described, and some of the fundamental limitations are addressed. The system presented in this paper can be directly used as a configuration of switching elements for the 2-D optical perfect-shuffle dynamic interconnection network, as well as for a B-ISDN photonic switching system.