• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.31 no.3A
• /
• pp.368-376
• /
• 2006

This paper describes a Fcore_GenSim(Parameterized FFT Core Generation & Simulation Program), which can be used as an essential If(Intellectual Property) in various OFDM modem designs. The Fcore_Gensim is composed of two parts, a parameterized core generator(PFFT_CoreGen) that generates Verilog-HDL models of FFT cores, and a fixed-point FFT simulator(FXP_FFTSim) which can be used to estimate the SQNR performance of the generated cores. The parameters that can be specified for core generation are FFT length in the range of 64 ~2048-point and word-lengths of input/output/internal/twiddle data in the range of 8-b "24-b with 2-b step. Total 43,659 FFT cores can be generated by Fcore_Gensim. In addition, CBFP(Convergent Block Floating Point) scaling can be optionally specified. To achieve an optimized hardware and SQNR performance of the generated core, a hybrid structure of R2SDF and R2SDC stages and a hybrid algorithm of radix-2, radix-2/4, radix-2/4/8 are adopted according to FFT length and CBFP scaling.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.05a
• /
• pp.670-673
• /
• 2008

Optimized algorithms and numerical expressions which had been verified through C program simulation, should be analyzed again with HDL (hardware description language) such as Verilog, so that the verified ones could be modified to be applied directly to hardware implementation. The reason is that the characteristics of C programming language design is intrinsically different from the hardware design structure. The hardware IP verified doubly in view of hardware structure together with algorithmic verification, was implemented on the Altera Excalibur FPGA device equipped with ARM9 microprocessor core, to a real chip prototype, using Altera embedded system development tool kit. The implemented finite field calculation IPs can be used as library modules as Elliptic Curve Cryptography finite field operations which has more than 193 bit key length.

• Journal of Information Technology and Architecture
• /
• v.11 no.4
• /
• pp.495-504
• /
• 2014

This paper present a strategy of intellectual property acquisition and core technology development direction using analysis of 2D to 3D video conversion technology patent data. As a result of analysis of trends in patent 2D to 3D technology, it is very promising technology field. Using a strategic patent map using research of patent trend, you will keep ahead of the competition in 2D3D image data conversion market.

• Journal of the Korean Society for information Management
• /
• v.32 no.1
• /
• pp.265-295
• /
• 2015

Digital curation can be said that the new information management and services in the digital age. In terms of exploring the systematic management and services for the information resources in the digital environment, Digital curation is one the core areas of library and information science. This study was set up a research areas as a result of reviewing the related literatures, and analyzed the research trends to the scholarly articles retrieved from a representative databases in the areas of Library and Information Science (LISTA). Also, I suggested future research agendas for digital curation in the areas of library and information science based on the results of the this analysis.

• Steel and Composite Structures
• /
• v.13 no.5
• /
• pp.409-421
• /
• 2012

Recently, as the height of building is getting higher, the applications of CFST column for high-rise buildings have been increased. In structural system of high-rise building, The RC core and exterior concrete-filled tubular (CFST) column-beam pinned connection is one of the structural systems that support lateral load. If this structural system is used, due to the minimal CFST column thickness compared to that of the CFST column width, the local moment occurred by the eccentric distance between the column flange surface from shear bolts joints degrades the shear strength of the CFST column-beam pinned connections. This study performed a finite element analysis to investigate the shear strength under eccentric moment of the CFST column-beam pinned connections. The column's width and thickness were used as variables for the analysis. To guarantee the reliability of the finite element analysis, an actual-size specimens were fabricated and tested. The yield line theory was used to formulate an shear strength formula for the CFT column-beam pinned connection. the shear strength formula was suggested through comparison on the results of FEM analysis, test and yield lime theory, the shear strength formula was suggested.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2011.05a
• /
• pp.769-770
• /
• 2011

This paper presented a method constructing the ITSoC(Information Technology System-on-Chip). In order to implement the ITSoC, designers are increasing relying on reuse of intellectual property(IP) blocks. Since IP blocks are pre-designed and pre-verified, the designer can concentrate on the complete system without having to worry about the correctness or performance of the individual components. Also, embedded core in an ITSoC access mechanisms are required to test them at the system level. That is the goal, in theory. In practice, assembling an ITSoC using IP blocks is still an error-prone, labor-intensive and time-consuming process. This paper discuss the main challenge in ITSoC designs using IP blocks and elaborates on the methodology and tools being put in place for addressing the problem. It explains ITSoC architecture and gives algorithmic details on the high-level tools being developed for ITSoC design.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.6
• /
• pp.1323-1332
• /
• 2005

EAP (Extensible authentication protocol) is a sort of general framework for authentication rather than a specific authentication protocol. An important consequence of this is that EAP can accommodate a variety of authentication/key-establishment protocols for different internet access networks possibly integrated to a common IP core network This paper tries a comparative analysis of several specific authentication/key establishment protocols for EAP, and suggest a strategic viewpoint toward the question: which one to un. In addition, we tried to make things clear about an intellectual property right issue with regard to some password-based protocols.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.16 no.3
• /
• pp.359-366
• /
• 2016

Today's multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role. This paper proposes a novel multicast routing technique entitled as Docket NoC (Dt-NoC), which eliminates the need of routing tables for faster communication. This technique reduces the latency and computing power of NoC. This work uses a CURVE restriction based algorithm to restrict few CURVES during the communication between source and destination and it prevents the network from deadlock and livelock. Performance evaluation is done by utilizing cycle accurate RTL simulator and by Cadence TSMC 18 nm technology. Experimental results show that the Dt-NoC architecture consumes power approximately 33.75% 27.65% and 24.85% less than Baseline XY, EnA, OEnA architectures respectively. Dt-NoC performs good as compared to other routing algorithms such as baseline XY, EnA, OEnA distributed architecture in terms of latency, power and throughput.

• Journal of Korean Society of Industrial and Systems Engineering
• /
• v.44 no.3
• /
• pp.125-132
• /
• 2021

In this study, the improvement of the IP system, which is the core infrastructure of the MRO project, and its effect were analyzed. Systematic problems and problems that are not competitive in the actual operating environment were systematically derived, and based on this, the most suitable method for target system development was found and improved. And the data of the improved system was analyzed and the effect was verified through empirical analysis of the system improvement effect through the user questionnaire. As a result of the study, the item with the highest improvement effect was convenience, which increased by 12.43 points. Then it increased by 10.25 points in terms of features. In particular, you will notice a significant improvement in speed by 30-50%. This is because the empirical analysis results are more objective and realistic than other conceptual models. Also, from the practical point of view, based on the results of the empirical analysis, corporate management can more effectively promote the intellectual property system, which is expected to contribute to the enhancement of corporate competitiveness.

• Journal of Information Processing Systems
• /
• v.15 no.2
• /
• pp.374-385
• /
• 2019

This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.