• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.348-348
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• 2008

In recent, the concept of system-on-package (SOP) for highly integrated multifunctional systems has been paid attention to for the miniaturization and high frequency of electronic devices. In order to realize SOP, co-integration of passive devices, such as capacitors, resistors and inductors, and active devices should be achieved. If ceramic thick films can be grown at room temperature, we expect to be able to overcome many problems in conventional fabrication processes. So, we focused on the aerosol deposition method (ADM) as room temperature fabrication technology. ADM is a novel ceramic coating method based on the Room Temperature Impact Consolidation (RTIC) phenomena. This method has a wide range potential for fabrication of co-integration of passive and active devices. In this paper, I will present the future potential of ADM introducing various ceramic dielectric thick films for the integration of electronic ceramics.

• Electronics and Telecommunications Trends
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• v.32 no.6
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• pp.8-16
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• 2017

In this paper, we review studies attempting to triumph over the limitation of Si-based semiconductor technologies through a heterogeneous integration of high mobility compound semiconductors on a Si substrate, and the co-integration of electronic and/or optical devices. Many studies have been conducted on the heterogeneous integration of various materials to overcome the Si semiconductor performance and obtain multi-purpose functional devices. On the other hand, many research groups have invented device fusion technologies of electrical and optical devices on a Si substrate. They have co-integrated Si-based CMOS and InGaAs-based optical devices, and Ge-based electrical and optical devices. In addition, chip and wafer bonding techniques through TSV and TOV have been introduced for the co-integration of electrical and optical devices. Such intensive studies will continue to overcome the device-scaling limitation and short-channel effects of a MOS transistor that Si devices have faced using a heterogeneous integration of Si and a high mobility compound semiconductor on the same chip and/or wafer.

• Journal of the Microelectronics and Packaging Society
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• v.22 no.2
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• pp.11-19
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• 2015

Since CMOS device scaling has stalled, three-dimensional (3-D) integration allows extending Moore's law to ever high density, higher functionality, higher performance, and more diversed materials and devices to be integrated with lower cost. 3-D integration has many benefits such as increased multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging volume, because it vertically stacks multiple materials, technologies, and functional components such as processor, memory, sensors, logic, analog, and power ICs into one stacked chip. Anticipated applications start with memory, handheld devices, and high-performance computers and especially extend to multifunctional convengence systems such as cloud networking for internet of things, exascale computing for big data server, electrical vehicle system for future automotive, radioactivity safety system, energy harvesting system and, wireless implantable medical system by flexible heterogeneous integrations involving CMOS, MEMS, sensors and photonic circuits. However, heterogeneous integration of different functional devices has many technical challenges owing to various types of size, thickness, and substrate of different functional devices, because they were fabricated by different technologies. This paper describes new 3-D heterogeneous integration technologies of chip self-assembling stacking and 3-D heterogeneous opto-electronics integration, backside TSV fabrication developed by Tohoku University for multifunctional convergence systems. The paper introduce a high speed sensing, highly parallel processing image sensor system comprising a 3-D stacked image sensor with extremely fast signal sensing and processing speed and a 3-D stacked microprocessor with a self-test and self-repair function for autonomous driving assist fabricated by 3-D heterogeneous integration technologies.

• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.3
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• pp.133-139
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• 2007

Future MEMS systems will be composed of larger varieties of devices with very different functionality such as electronics, mechanics, optics and bio-chemistry. Integration technology of heterogeneous devices must be developed. This article first deals with the current development trend of new fabrication technologies; those include self-assembling of parts over a large area, wafer-scale encapsulation by wafer-bonding, nano imprinting, and roll-to-roll printing. In the latter half of the article, the concept towards the heterogeneous integration of devices and functionality into micro/nano systems is described. The key idea is to combine the conventional top-down technologies and the novel bottom-up technologies for building nano systems. A simple example is the carbon nano tube interconnection that is grown in the via-hole of a VLSI chip. In the laboratory level, the position-specific self-assembly of nano parts on a DNA template was demonstrated through hybridization of probe DNA segments attached to the parts. Also, bio molecular motors were incorporated in a micro fluidic system and utilized as a nano actuator for transporting objects in the channel.

• Journal of Sensor Science and Technology
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• v.31 no.2
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• pp.71-78
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• 2022

Wearable devices have the potential to revolutionize future medical diagnostics and personal healthcare. The integration of biosensors into scalable form factors allow continuous and noninvasive monitoring of key biomarkers and various physiological indicators. However, conventional wearable devices have critical limitations owing to their rigid and obtrusive interfaces. Recent developments in functional biocompatible materials, micro/nanofabrication methods, multimodal sensor mechanisms, and device integration technologies have provided the foundation for novel skin-interfaced bioelectronics for advanced and user-friendly wearable devices. Nonetheless, it is a great challenge to satisfy a wide range of design parameters in fabricating an authentic skin-interfaced device while maintaining its edge over conventional devices. This review highlights recent advances in skin-compatible materials, biosensor performance, and energy-harvesting methods that shed light on the future of wearable devices for digital health and personalized medicine.

• Journal of IKEEE
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• v.23 no.1
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• pp.326-329
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• 2019

Gallium nitride(GaN) has been a superior candidate for the next generation power electronics. As GaN-on-Si substrate technology is mature, there has been new demand for monolithic integration of GaN technology with Si CMOS devices. In this work, (110)Si CMOS process was developed and the fabricated devices were evaluated in order to confirm the feasibility of utilizing domestic foundry facility for monolithic integration of Si CMOS and GaN power devices.

• The Proceeding of the Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.2
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• pp.23-34
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• 2013

Over the past several decades in the microelectronics industry, devices have gotten smaller, thinner, and lighter, without any accompanying degradation in quality, performance, and reliability. One permanent and deniable trend in packaging as well as wafer fabrication industry is system integration. The proliferating options for system integration, recently, are driving change across the overall semiconductor industry, requiring more investment in developing, ramping and supporting new die-, wafer- and board-level solution. The trend toward 3D system integration and miniaturization in a small form factor has accelerated even more with the introduction of smartphones and tablets. In this paper, the key issues and state of the art for system integration in the packaging process are introduced, especially, focusing on ease transition to next generation packaging technologies like through silicon via (TSV), 3D wafer-level fan-out (WLFO), and chip-on-chip interconnection. In addition, effective solutions like fine pitch copper pillar and MEMS packaing of both advanced and legacy products are described with several examples.

• Proceedings of the Materials Research Society of Korea Conference
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• 2010.05a
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• pp.30.2-30.2
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• 2010

Nano-scale p-n junction can generate various nano-scale functional devices such as nanowire light emitting diode, nanowire solar cell, and nanowire sensor. The core shell type nanowire p-n junction has been considered for the high efficient devices in many previous reports. On the other hand, although device efficiency is relatively lower, the cross bar type p-n junction has simple topological structure, suggested by C.M. Lieber group, to integrate easily many p-n junction devices in one board. In this study, for the integration of the cross bar nanowire p-n junction device, a simple fabrication route, employed dielectrophoretic array and direct printing techniques, was demonstrated by the successful fabrication and programmable integration of the nanowire cross bar p-n junction solar cell. This direct printing process will give the single nanowire solar cell the opportunity of the integration on the circuit board with other nanowire functional devices.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.3
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• pp.1313-1318
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• 2011

This paper proposes a protocol integration system with multi-threading method for the ship electronic devices to solve problems with the compatibility. The proposed protocol integration system receives the different signals from each of the ships' devices through the RS-232 serial communication port and then divides the input signal into the field data. The required field data for standard signal composition are extracted from among these signal and these are combined in accordance with standard signal format. Thereafter, the protocol integration system transmits the processed standard signal to the auto pilot system through a single port.