• 대한기계학회논문집B
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• 제41권6호
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• pp.409-414
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• 2017

본 연구의 목적은 실제 실리콘 박막 트랜지스터 내 포논 전달 특성을 이해하는 것이다. 이를 위해 박막 소자 내 열해석 예측 정확성이 검증된 전자-포논 상호작용 모델을 이용하여 반도체 산업에서 중요한 Silicon-on-Insulator(SOI) 시스템에 대한 다양한 조건에서 전자-포논 산란에 의한 Joule 가열 메커니즘의 고려하여 포논 전달 해석을 수행했다. 소자 장치 전원(device power)과 실리콘 층 두께 변화에 따른 포논의 평균자유행로(mean free path) 스펙트럼에 대한 열적 특성을 조사하여, 실제 SOI 소자 내 포논 전달을 이해했다. 이 결과는 SOI 소자의 신뢰성 설계 및 고효율 열소산(heat dissipation) 설계전략에 필요한 포논 전달 특성 이해에 활용될 수 있다.

• 대한기계학회논문집B
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• 제30권6호
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• pp.594-601
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• 2006

Optimization study has been carried out to design an energy efficient, high temperature vacuum furnace which satisfies users' design requirements. First of all, the transient temperature distribution and the uniform temperature zone results have been compared with the steady state results to validate the feasibility of using steady state solution when constructing the thermal analysis DB. In order to check the accuracy, the interpolated results using thermal analysis DB have been compared with the computational and the experimental results. In this study, total heat flux is selected as the objective function, and the geometry parameters of vacuum furnace including the thickness of insulator, the heat zone sizes and the interval between heater and insulator are the design variables. The Uniform temperature zone sizes and the wall temperature are imposed as the design constraints. With negligible computational cost a high temperature vacuum furnace which has $40\sim60%$ reduction in total heat flux is designed using thermal analysis DB.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.10-10
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• 2010

ESD (Electrostatic Discharge) phenomenon occurs in everywhere and especially it damages to semiconductor devices. For ESD protection, there are some devices such as diode, GGNMOS (Gate-Grounded NMOS), SCR (Silicon-Controlled Rectifier), etc. Among them, diode and GGNMOS are usually chosen because of their small size, even though SCR has greater current capability than GGNMOS. In this paper, a novel SCR is proposed on the SOI (Silicon-On-Insulator) structure which has $1{\mu}m$ film thickness. In order to design and confirm the proposed SCR, TSUPREM4 and MEDICI simulators are used, respectively. According to the simulation result, although the proposed SCR has more compact size, it's electrical performance is better than electrical characteristics of conventional GGNMOS.

• JSTS:Journal of Semiconductor Technology and Science
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• 제5권2호
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• pp.136-147
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• 2005

A theoretical design evaluation based on a hydrodynamic transport simulation of strained Si-SiGe on insulator (SSOI) type nMOSFETs is reported. Although, the net performance improvement is quite limited by the short channel effects, simulation results clearly show that the strained Si-SiGe type nMOSFETs are well-suited for gate lengths down to 20 nm. Simulation results show that the improvement in the transconductance with decreasing gate length is limited by the long-range Coulomb scattering. An influence of lateral and vertical diffusion of shallow dopants in the source/drain extension regions on the device performance (i.e., threshold voltage shift, subthreshold slope, current drivability and transconductance) is quantitatively assessed. An optimum layer thickness ($t_{si}$ of 5 and $t_{sg}$ of 10 nm) with shallow Junction depth (5-10 nm) and controlled lateral diffusion with steep doping gradient is needed to realize the sub-50 nm gate strained Si-SiGe type nMOSFETs.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 춘계학술대회 논문집 유기절연재료 전자세라믹 방전플라즈마 연구회
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• pp.59-61
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• 2001

Polymeric suspended insulators for the electric track line have been developed. The main elements to design polymeric insulators are the insulation ability related with materials of FRP core and housing, and the optimal structure related with fitting parts and interface characteristics. To confirm the design fitness of insulator samples the electric field distribution by FEM and mechanical stress distribution by NASTRAN program was analysed with housing shed shapes and fitting structure. The leakage distance and breakage voltage properties which are core parameters to determine electric insulation ability are selected according to the requirement values of user specification, then the power frequency wet withstand voltage was specified above 22kV and the leakage distance was required above 290mm. The contamination condition of the electric track line was the heavy class according to IEC 815 in order to retain the enough safety margin against overvoltages.

• 한국정밀공학회:학술대회논문집
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• 한국정밀공학회 2013년도 춘계학술대회 논문집
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• pp.1207-1208
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• 2013

• 대한기계학회논문집B
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• 제40권2호
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• pp.111-117
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• 2016

본 연구의 목적은 실리콘 열전달 조절을 위한 포논의 평균자유행로(Mean free path, MFP) 스펙트럼 열전달 기여도 예측이다. 열전달의 크기 효과는 포논의 MFP 와 재료의 특성길이가 비슷할 때 나타나는데, 나노시스템 응용을 위한 재료의 열전달 증감을 위해 포논 MFP 스펙트럼에 대한 열전달 기여도 예측이 중요하다. 이를 위해 포논의 주파수 의존성이 고려된 볼츠만 수송방정식(Boltzmann transport equation) 근간의 full phonon dispersion 모델을 통해 실리콘 박막(Silicon-on-Insulator) 트랜지스터의 실리콘 박막 두께 변화(41-177 nm)에 따른 포논 MFP 스펙트럼 열전달 특성 및 비등방성을 해석함으로써, 본 연구 결과는 향후 박막 트랜지스터에 대한 고효율 열소산(heat dissipation) 설계전략에 활용될 수 있다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집 Vol.3 No.2
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• pp.935-938
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• 2002

The degree of contamination in outdoor insulation system is one of the most importance factor to determine the level of insulation, and the salt is known as the most dangerous contaminants in the most region of the world. In a macroscopic point of view, as shown through the preceding study, the generation and deposition of salt contaminants has a great relation with the geographical conditions and the meteorological conditions, such as, wind velocity, wind direction, precipitation and so forth. However, in the aspect of microscopic analysis, the pollution mechanism has a great relation with aerodynamic properties of insulator, originated from the profile of insulators, and the non-uniform deposition is unevitable. So, in this investigation, we had make a experiment to seize the electrical properties of non-uniformly contaminated insulator. The results of this investigation could be used as a good groundwork in the determination of outdoor insulation design.

• 센서학회지
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• 제25권3호
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• pp.229-234
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• 2016

Self-powered neutron detector (SPND) is being widely used to monitor the reactor core of the nuclear power plants. The SPND contains a neutron-sensitive metallic emitter surrounded by a ceramic insulator. Currently, the vanadium (V) SPND has been being developed to be used in OPR1000 nuclear power plants. Some Monte Carlo simulations were accomplished to calculate the initial sensitivity of vanadium emitter material and alumina insulator with a cylindrical geometry. An MCNP code was used to simulate some factors (neutron self-shielding factor and beta escape probability from the emitter) and space charge effect of an insulator necessary to calculate the sensitivity of vanadium detector. The simulation results were compared with some theoretical and experimental values. The method presented here can be used to analyze the optimum design of the vanadium SPND and contribute to the development of TMI (Top-mount In-core Instrumentation) which might be used in the SMART and SMR.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.519-525
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• 2015

Positive bias stress-induced instability in amorphous indium-gallium-zinc-oxide (a-IGZO) bottom-gate thin-film transistors (TFTs) was investigated under high $V_{GS}$/low $V_{DS}$ and low $V_{GS}$/high $V_{DS}$ stress conditions through incorporating a forward/reverse $V_{GS}$ sweep and a low/high $V_{DS}$ read-out conditions. Our results showed that the electron trapping into the gate insulator dominantly occurs when high $V_{GS}$/low $V_{DS}$ stress is applied. On the other hand, when low $V_{GS}$/high $V_{DS}$ stress is applied, it was found that holes are uniformly trapped into the etch stopper and electrons are locally trapped into the gate insulator simultaneously. During a recovery after the high $V_{GS}$/low $V_{DS}$ stress, the trapped electrons were detrapped from the gate insulator. In the case of recovery after the low $V_{GS}$/high $V_{DS}$ stress, it was observed that the electrons in the gate insulator diffuse to a direction toward the source electrode and the holes were detrapped to out of the etch stopper. Also, we found that the potential profile in the a-IGZO bottom-gate TFT becomes complicatedly modulated during the positive $V_{GS}/V_{DS}$ stress and the recovery causing various threshold voltages and subthreshold swings under various read-out conditions, and this modulation needs to be fully considered in the design of oxide TFT-based active matrix organic light emitting diode display backplane.