• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.33 no.4
• /
• pp.286-290
• /
• 2020

The formation of inorganic thin films in low-temperature solution processes is necessary for a wide range of commercial applications of organic electronic devices. Aluminum oxide thin films can be utilized as barrier films that prevent the deterioration of an electronic device due to moisture and oxygen in the air. In addition, they can be used as the gate insulating layers of a thin film transistor. In this study, aluminum oxide thin film were formed using two methods simultaneously, a thermal process and the DUV process, and the properties of the thin films were compared. The result of converting aluminum nitrate hydrate to aluminum oxide through a hybrid process using a thermal treatment and DUV was confirmed by XPS measurements. A film-based a-IGZO TFT was fabricated using the formed inorganic thin film as a gate insulating film to confirm its properties.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.811-816
• /
• 2019

The silicon-adsorbed oxygen(Si-O) superlattice grown by ultra high vacuum-chemical vapor deposition(UHV-CVD) was introduced as an epitaxial barrier for silicon quantum electron devices. The current-voltage (I-V) measurement results show the stable and good insulating behavior with high breakdown voltage. It is apparent that the Si-O superlattice can serve as an epitaxially grown insulating layer as possible replacement of silicon-on-insulator(SOI). This thick barrier may be useful as an epitaxial insulating gate for field effect transistors(FETs). The rationale is that it should be possible to fabricate a FET on top of another FET, moving one step closer to the ultimate goal of future silicon-based three-dimensional integrated circuit(3DIC).

• Journal of Electrical Engineering and Technology
• /
• v.10 no.3
• /
• pp.1114-1123
• /
• 2015

Bushing is the key link to connect outer and inner insulating systems and also the essential electric accessory in electric power system, especially in the high voltage engineering (AC 1000kV, DC 800kV). This paper presented the experimental research of thermal aging characteristic of oil-paper insulation used in bushing. A thermally accelerated aging experiment at 90℃ was performed. The bushing models containing five layers of paper were sealed into the aging vessels and further aged for 250 days. Then several important parameters associated with the aging were observed and evaluated. The results showed that the degree of polymerization (DP) of papers gradually decreased. The DP values of outermost layer and middle layer fit well into the second-order kinematic model and first-order kinematic model, respectively. Less deterioration speed of the inter-layer paper than outer layer was confirmed by the variation of DP. Hydrolysis was considered as the main cause to this phenomenon. In addition, the logarithm of the furfural concentrations in insulation oil was found to have good linear relationship with DP of papers. Interestingly, when the aging time is about 250 days and DP is 419, the aging process reaches an inflection point at which the DP approaches the leveling off degree of polymerization (LODP) value. Both tanδ and acid number of oils increased, while surface and volume resistivity of papers decreased. The obtained results demonstrated that thermal aging and moisture absorbed in papers brought great influence to the degradation of insulating paper, leading to rapid decrease of DP and increase of the tanδ. Thus, the bushing should be avoided from damp and real-time monitoring to the variation of tanδ and DP values of paper is an effective way to evaluate the insulation status of bushing.

• Journal of Adhesion and Interface
• /
• v.22 no.4
• /
• pp.153-157
• /
• 2021

Graphene, a two-dimensional carbon allotrope, has outstanding mechanical and electrical properties. In particular, the charge carrier mobility of graphene is known to be about 100 times higher than that of silicon, and it has received attention as a core material for next-generation electronic devices. However, graphene is very sensitive to environmental conditions, especially vulnerable to moisture or oxygen. It becomes a disadvantage in that the stability of the graphene-based electronic device, so various attempts are being made to solve this problem. In this work, we report a method to greatly improve the stability by controlling the surface energy of the polymer layer used for transferring the insulating layer of the graphene field-effect transistor. As the surface energy of the polymer used as the insulating layer was lowered, the stability could be improved by effectively controlling the adsorption of impurities in the atmosphere such as water molecules or oxygen.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2005.07b
• /
• pp.940-943
• /
• 2005

The characteristics of a-Si:H TFTs with silicon oxide as passivation layer were reported. It was studied that the insulating characteristics and step coverage characteristics of low temperature silicon oxide before applying to a-Si:H TFT fabrications. With the optimum deposition conditions considering electrical and deposition characteristics, low temperature silicon oxide was applied to a-Si:H TFTs. The changes in characteristics of a-Si:H TFTs were analyzed after replacing silicon nitride passivation layer with low temperature silicon oxide layer. This low temperature silicon oxide can be adapted to high resolution a-Si:H TFT LCD panels.

• Proceedings of the KIEE Conference
• /
• 1997.07d
• /
• pp.1621-1623
• /
• 1997

The breakdown voltage of SOI RESURF (REduce SURface Field) diode using a SIPOS (Semi Insulating POlycrystalline Silicon) layer is verified in terms of n-drift layer length and surface oxide thickness by device simulator MEDICI, and compared with conventional SOI RESURF diode. Increasing the n-drift layer length, the breakdown voltage of SOI RESURF diode using the SIPOS layer have increased and saturated at $8{\mu}m$. And it has decreased with increasing the surface oxide thickness.

• Proceedings of the Korea Institute of Applied Superconductivity and Cryogenics Conference
• /
• 2003.10a
• /
• pp.263-268
• /
• 2003

The Electrical insulation design and testing of high temperature superconducting (HTS) coil for high temperature superconducting fault current limiter (HTSFCL) has been performed. Electrical insulating factors of HTS coil for HTSFCL are turn-to-turn, layer-to-layer. The electrical insulation of turn-to-turn depends on surface length, and the electrical insulation of layer-to-layer depends on surface length and breakdown strength of L$N_2$. Therefore, two basic characteristics of breakdown and flashover voltage were experimentally investigated to design electrical insulation for 6.6㎸ Class HTSFCL. We used Weibull distribution to set electric field strength for insulation design. And mini-model HTS coil for HTSFCL was designed by using Weibull distribution and was manufactured to investigate breakdown characteristics. The mini-model HTS coil had passed in AC and Impulse withstand test.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.55 no.1
• /
• pp.26-29
• /
• 2006

Transparent ZnO thin films were prepared by KrF pulsed laser deposition (PLD) technique and applied to a bottom-gate type thin film transistor device as an active channel layer. A high conductive crystalline Si substrate was used as an metal-like bottom gate and SiN insulating layer was then deposited by LPCVD(low pressure chemical vapour deposition). An aluminum layer was then vacuum evaporated and patterned to form a source/drain metal contact. Oxygen partial pressure and substrate temperature were varied during the ZnO PLD deposition process and their influence on the thin film properties were investigated by X-ray diffraction(XRD) and Hall-van der Pauw method. Optical transparency of the ZnO thin film was analyzed by UV-visible phometer. The resulting ZnO-TFT devices showed an on-off ration of $10^6$ and field effect mobility of 2.4-6.1 $cm^2/V{\cdot}s$.

• Structural Engineering and Mechanics
• /
• v.83 no.1
• /
• pp.67-77
• /
• 2022

In this study, frictionless continuous and discontinuous contact problems of a magneto-electro-elastic layer in the presence of the body force were discussed. The layer was indented by a rigid cylindrical insulating punch and supported by a rigid substrate without bond. Applying the Fourier integral transform technique, the general expressions of the problem were derived in the presence of body force. Thanks to the boundary conditions, the singular integral equations were obtained for both the continuous and the discontinuous contact cases. Gauss-Chebyshev integration formulas were used to transform the singular integral equations into a set of nonlinear equations. Contact width under the punch, initial separation distance, critical load, separation regions and contact stress under the punch and between the layer, and substrate were given as a result.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.18 no.5
• /
• pp.475-480
• /
• 2017

In this paper, the conductivity of the fine pattern is improved in the insulating substrate by laser-induced forward transfer (LIFT) process. The high laser beam energy generated in conventional laser induced deposition processes induces problems such as low deposition density and oxidation of micro-patterns. These problems were improved by using a polymer coating layer for improved deposition accuracy and conductivity. Chromium and copper were used to deposit micro-patterns on silicon wafers. A multi-pulse laser beam was irradiated on a metal thin film to form a seed layer on an insulating substrate(SiO2) and electroless plating was applied on the seed layer to form a micro-pattern and structure. Irradiating the laser beam with multiple scanning method revealed that the energy of the laser beam improved the deposition density and the surface quality of the deposition layer and that the electric conductivity can be used as the microelectrode pattern. Measuring the resistivity after depositing the microelectrode by using the laser direct drawing method and electroless plating indicated that the resistivity of the microelectrode pattern was $6.4{\Omega}$, the resistance after plating was $2.6{\Omega}$, and the surface texture of the microelectrode pattern was uniformly deposited. Because the surface texture was uniform and densely deposited, the electrical conductivity was improved about three fold.