• Proceedings of the IEEK Conference
• /
• 2001.06b
• /
• pp.105-108
• /
• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Information and Communications Magazine
• /
• v.25 no.12
• /
• pp.10-18
• /
• 2008

In this paper, we present a low-power design of H.264 codec based on dedicated hardware and software solution on EMP(ETRI Multi-core platform). The dedicated hardware scheme has reducing computation using motion estimation skip and reducing memory access for motion estimation. The design reduces data transfer load to 66% compared to conventional method. The gate count of H.264 encoder and the performance is about 455k and 43Mhz@30fps with D1(720x480) for H.264 encoder. The software solution is with ASIP(Application Specific Instruction Processor) that it is SIMD(Single Instruction Multiple Data), Dual Issue VLIW(Very Long Instruction Word) core, specified register file for SIMD, internal memory and data memory access for memory controller, 6 step pipeline, and 32 bits bus width. Performance and gate count is 400MHz@30fps with CIF(Common Intermediated format) and about 100k per core for H.264 decoder.

• Journal of Korean Library and Information Science Society
• /
• v.28
• /
• pp.93-135
• /
• 1998

The purpose of this study was to compare the effectiveness of programmed instruction versus lecture and discussion method on the knowledge of basic reference sources among undergraduate library and information science students. The hypotheses of the study were: 1. Programmed instruction will be more effective than the lecture/discussion method with regard to academic achievement. 2. There will be a significant difference in learning time between the experimental and the control groups. Seventy-eight library and information science students were participated m the study from the two universities in Chungchong Province. A programmed instruction manual, including 4-types of reference sources-dictionary, encyclopaedia, bibliography, indexes and abstracts, 40-item multiple choice post-test, and a questionnaire for the students' attitude toward programmed instruction were developed specifically for this research. The post-test only control-group design was selected for this experimental study. Students were given instruction on the specific reference titles in dictionary, encyclopedia, bibliography, indexes and abstracts. The control group was instructed by the lecture and discussion method while the experimental group completed a programmed instruction manual by themselves. Both the control and the experimental group were tested right after the instruction of 4-types of reference sources. In addition, a questionnaire asking students' attitude toward programmed instruction was administered to the experimental group. The findings from this study are summarized as follows: 1. The results showed that there were no significant difference in the mean of the post test score between the two groups. Therefore, programmed instruction is viable as an alternative method of instruction in the teaching of reference sources. 2. There was a significant difference in the mean of time spending for the leaning of bibliography, indexes and abstracts between the two groups. Accordingly, programmed instruction proved to be more efficient than the conventional lecture/discussion method in terms of learning time. 3. Students showed positive response to programmed instruction and evaluated it very interesting and challenging. In conclusion, the programmed instruction method was just as effective as the lecture/discussion method in the teaching of reference sources. And students' attitude toward the programmed instruction was favorable enough to secure a continued use of this method for the teaching of reference sources.

• Journal of the Korea Society for Simulation
• /
• v.12 no.2
• /
• pp.45-53
• /
• 2003

This paper presents a retargetable compiled assembly simulation technique for fast ASIP(application specific instruction processor) simulation. Development of ASIP which satisfies design requirements in various fields of applications such as telecommunication, wireless network, etc. needs formal design methodology and high-performance relevant software environments such as compiler and simulator In this paper, we employ the architecture description language(ADL) named ${HiXR}^2$ to automatically synthesize an instruction-level compiled assembly simulator. A compiled simulation has benefit of time efficiency to interpretive one because it performs instruction fetching and decoding at compile time. Especially, in case of assembly simulation, instruction decoding is usually a time-consuming job(string operation), so the compiled simulation of assembly simulation is more efficient than that of binary simulation. Performance improvement of the compiled assembly simulation based on ${HiXR}^2$ is exemplified with an ARM9 architecture and a CalmRISC32 architecture. As a result, the compiled simulation is about 150 times faster than interpretive one.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.27 no.7
• /
• pp.1015-1024
• /
• 1990

This paper proposes a program counter unit(PCU) on the pipelined architecture of RISC (Reduced Instruction Set Computer) type high performance processors, PCU is used for supplying instruction addresses to memory units(Instruction Cache) efficiently. A RISC processor's PCU has to compute the instruction address within required intervals continnously. So, using the method of self-generated incrementor, is more efficient than the conventional one's using ALU or private adder. The proposed PCU is designed to have the fast +4(Byte Address) operation incrementor that has no carry propagation delay. Design specifications are taken by analyzing the whole data path operation of target processor's default and exceptional mode instructions. CMOS and wired logic circuit technologic are used in PCU for the fast operation which has small layout area and power dissipation. The schematic capture and logic, timing simulation of proposed PCU are performed on Apollo W/S using Mentor Graphics CAD tooks.

• Journal of Multimedia Information System
• /
• v.8 no.4
• /
• pp.243-250
• /
• 2021

Instructional contents are used to demonstrate a technical process to teach and walkthrough certain procedures to carry out a task. This type of informational content is widely used for teaching and lectures in form of tutorial videos and training videos. Since there are questions and uncertainties for what could be the killer application for the novel wearables, we propose a self-instruction training application on a smart glass to utilize already-available instruction videos as well as public open data in creative ways. We design and implement a prototype application to help users train by wearing smart glasses specifically designed for two concrete and hand-constrained use cases where the user's hands need to be free to operate. To increase the efficiency and feasibility of the self-instruction training, we contribute to the development of a wearable killer application by integrating a voice-based user interface using speech recognizer, public open data APIs, and timestamp-based procedural content navigation structure into our proof-of-concept application.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.05a
• /
• pp.281-284
• /
• 2008

Recently, Khronos institude OpenGL ES 2.0 API for support Shader 3.0 model that can possible variable graphic processing. For this reason, the mobile device have need of supporting processor for a shader 3.0 model. We should extend instruction's length to support OpenGL ES 2.0 API, so we need more memory size. In this paper, we propose a new instruction form that adopted variable length and unit instruction architecture. This proposed instruction architecture that support to Shader 3.0 model has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of the Korea Society of Computer and Information
• /
• v.18 no.7
• /
• pp.1-10
• /
• 2013

In this paper, the parallel branch instruction is proposed which executes a branch instruction and the frequently used instruction simultaneously to improve the performance of Thumb-2 instruction set architecture. In the proposed approach, new 32-bit parallel branch instructions are introduced which combine 16-bit branch instruction with each of the frequently used 16-bit LOAD, ADD, MOV, STORE, and SUB instructions, respectively. To provide the encoding space of the new instructions, the register field in less frequently executed instructions is reduced, and the new instructions are encoded by using the saved bits. Experiments show that the proposed approach improves performance by an average of 8.0% when compared to the conventional approach.

• Journal of IKEEE
• /
• v.12 no.2
• /
• pp.118-123
• /
• 2008

The Khronos group releases OpenGL ES 2.0 API specification bringing streamlined shader programming to graphics processor of embedded system. For this reason, the mobile devices have need of graphics processor for supporting a OpenGL ES 2.0 API. We need to extend instruction`s length to support OpenGLES 2.0 API, so it needs more memory size. In this paper, we propose a new instruction format that offers availability for use the instructions. This proposed instruction adopt a variable length method and unit instruction architecture. This proposed instruction architecture that support to OpenGLES 2.0 API has consist of 32bit unit instructions up to 4 which can be combined for embellishing each other. Therefore, it can execute flexible instruction combination and reduce waste of instruction fields.

• Journal of Digital Contents Society
• /
• v.6 no.4
• /
• pp.209-216
• /
• 2005

The aim of this study is to examine the effects of web-based cyber instruction on EFL learning from the viewpoint of learners` perceptions and needs. Data was collected through a questionnaire survey that was carried out with 709 undergraduate student enrolled in three cyber English courses offered at N university during the secind semester in 2004. The results of the study indicated that the learners exhibited a positive attitude towards web-based cyber instruction and considered it a paper educational method in the cyber age. However, the students perceived that web-based cyber instruction was not greatly satisfactory in terms of cultivating their English communicative competence or improving the language skills they needed. It was also found that cyber instruction was still teacher-dominant, lacking in interaction, which made the students passive recipients of informaton presented. In comparison with off-line instruction, cyber instruction was not particularly better in enhancing their motivation interest or concentration on class. To be more effective, cyber instruction needs to be equipped not only with a large variety of contents and class activities, but also with more exposure to authentic language by native English speakers. The finding of the investigation yield some implications for the design and development of web-based cyber EFL programs.