• Proceedings of the Korea Information Processing Society Conference
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• 2014.11a
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• pp.53-56
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• 2014

Application specific instruction-set processor (ASIP) is a suitable design choice for system designers who seek both flexibility to handle various applications in the domain together with the performance. Successful development of an ASIP, however, requires a software development kit (SDK) to be provided along with the processor. Synopsys Processor Designer is an ASIP development tool, which takes as input a set of files written in a high-level architecture description language called LISA (Language for Instruction Set Architecture), and generates SDK as well as RTL. Recently, they have added support for the generation of LLVM compiler backend, though some manual work is required. In this paper, we introduce some details in porting LLVM compiler to a custom processor architecture in Synopsys Processor Designer.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.357-360
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• 2001

As SOC design methodology becomes popular, processors, the essential core in embedded system are required to be designed fast and supported to customers with expansive behavior description. This paper presents new methodology to meet such goals with designer configurable instruction set simulator for processors. This paper proposes new language called PML(Processor Modeling Language), which is based on microprogramming scheme and is also successful in most behavior of processors. By using this, we can describe scalar processor very efficiently with by-far faster simulation speed in compared with HDL model.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.53-58
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• 2008

This paper proposes a new set of instructions to improve the packet processing capacity of a network processor. The proposed set of instructions is able to achieve more efficient packet processing by accelerating integration of packet headers. Furthermore, a hardware configuration dedicated to processing overlay instructions was designed to reduce additional hardware cost. For this purpose, the basic architecture for the network processor was designed using LISA and the overlay block was optimized based on the barrel shifter. The block was synthesized to compare the area and the operation delay, and allocated to a C-level macro function using the compiler known function (CKF). The improvement in performance was confirmed by comparing the execution cycle and the execution time of an application program. Experiments were conducted using the processor designer and the compiler designer from Coware. The result of synthesis with the TSMC ($0.25{\mu}m$) from Synopsys indicated a reduction in operation delay by 20.7% and an improvement in performance of 30.8% with the proposed set of instructions for the entire execution cycle.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.45 no.3
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• pp.142-148
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• 2008

Though a deblocking filter of H.264/AVC provides enhanced image quality by removing blocking artifact on block boundary, the complex filtering operation on this process is a dominant factor of the whole decoding time. In this paper, we designed an ASIP to accelerate deblocking filter operation with the proposed instruction set. We designed a processor based on a MIPS structure with LISA, simulated a deblocking later model, and compared the execution time on the proposed instruction set. In addition, we generated HDL model of the processor through CoWare's Processor Designer and synthesized with TSMC 0.25um CMOS cell library by Synopsys Design Compiler. As the result of the synthesis, the area and delay time increased 7.5% and 3.2%, respectively. However, due to the proposed instruction set, total execution performance is improved by 18.18% on average.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.21-29
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• 1995

In this paper, a independent and structured microassembler was designed for easily changing the system design, and for designing various microarchitecture. When the designer's hardware and microprogramming process were made concurrently, it is needed to easily change or improve the instruction set and executable code format. But this type of developed environment requires a high const and a large software system. A proposed microassembler was designed so the designer directly defines the microinstruction set and format to be executed. And we implemented a module from each part of the software, so it is now possible to use practically and upgrade the function of each part, First, the symbol was separated from the assembler. And then microinstruction was copied into it. The microinstruction format was designed using the defined language that was designed for free microinstruction. This was implemented in an IBM-PC by using the C-language, FLEX,and BISON.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.848-851
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• 1997

A graphic simulation program is developed to assimilate the remote dismantling process of research nuclear reactors. This program makes extensive use of a commercial robot graphic instruction program. Firstly, a realistic graphic model of research reactors are built along with various dismantling equipments. Using the graphic instruction languages provided by IGRIP, then, a graphic process simulation program is developed that operates interactively with the user. Consequently, it is made possible for a process designer to visualize an arbitrary dismantling sequence and interactively modify the process. It is expected that the developed system will be utilized as an effective operator aid in both design and execution phases of remote dismantling of research reactor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.12
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• pp.58-65
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• 2011

This paper presents an ASIP (Application-specific Instruction Processor) for motion estimation that employs specific IME instructions and its programmable and reconfigurable hardware architecture for various video codecs, such as H.264/AVC, MPEG4, etc. With the proposed specific instructions and variable point 2D SAD hardware accelerator, it can handle the real-time processing requirement of High Definition (HD) video. With the SAD unit and its parallel operations using pattern information, the proposed IME instructions support not only full search algorithms but also other fast search algorithms. The hardware size is 25.5K gates for each Processing Element Group (PEG) which has 128 SAD Processor Elements (PEs). The proposed ASIP has been verified by the Synopsys Processor Designer and implemented by the Design Compiler using the IBM 90nm process technology. The hardware size is 453K gates for the IME unit and the operating frequency is 188MHz for 1080p@30 frame in real time. The proposed ASIP can reduce the hardware size about 26% and the number of operation cycles about 18%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.1
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• pp.29-42
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• 1990

In this paper, We use the APL as IDL when simulation a 16-bit SIP. It was possible for IDL to represent and describe a structure of a H/W which other HDL have not. Because We partitioned whole system to various modules when desingning processor, We adpoted a direct decoding method. A designed each modules are executed according to 12-bit control word was inputed through experimental framework, Which were composed to symbolized instructions. In here, By setting instruction codes of the SIP using binary code, We composed instruction format and assembler instruction, and verified the SIP behaviour that try to implement by entering a presented instruction set through experimental framework. In a presented SIP, Because inputing program are a symbolized language, Designer and user will easily understand behaviour of system. Especially, Because we can immediatly specify a unit function within SIP, We will use variously and easily the library cell.

• The Korean Journal of Emergency Medical Services
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• v.23 no.1
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• pp.19-33
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• 2019

Purpose: The aim of this study was to provide basic data to aid in the effective adoption of the preceptor system for new paramedics by assessing the preceptor role awareness among senior 119 paramedics in the field. Methods: A questionnaire was administered to 182 senior paramedics who each had more than 3 years field experience. The questionnaire measuring preceptor role awareness was composed of 64 items with responses based on a 5 point Likert scale. Data were collected from July 31, 2018 to August 29, 2018, and were analyzed with IBM SPSS version 24.0. Results: The average score for preceptor role awareness was 3.87 (supervisor = 3.95, resource person = 3.88, role model = 3.85, and instruction designer = 3.81). There were significant differences in preceptor role awareness among the participants based on competence (p =.002) and clinical skill (p =.000). Also, there were high positive correlations between preceptor role awareness and its subdivision (p <.01). Conclusion: For effective operation of the preceptor system in the future, the preceptors' role as designers of instruction and role models should be enhanced, Also, future preceptors are very important in the improvement of competence and clinical skill in the preceptor system. Therefore, it is necessary to provide training that enables new preceptors to effectively adopt and operate the preceptor system.

• Journal of Distribution Science
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• v.16 no.7
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• pp.67-75
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• 2018

Purpose - In the 21st century, as information technology advances alongside the emergence of the 4th generation, industrial age, industrial environment has become individualized and customized. It is important to hire good quality employees for good service in the industry. The e-learning market is growing every year. Although e-learning companies are finding better quality employees in e-learning, it is not easy to find it. Companies also spend a lot of time and cost to find employee. On the employees side, they want to get a job freely when they want, but they cannot find their job easily. Furthermore, the labor market environment is changing fast. In the 4th generation, industrial age, employers require to find manpower whenever they need and want at little cost. So of their own accord, we have considered the necessity of management of human resources for employees and employers in e-learning. The purpose of this study is to propose a human cloud platform framework for enabling an efficient management of human resources in e-learning industry. Research design, data, and methodology - To pinpoint the items of a human cloud platform framework, the study was initiated according to the following process. First, items of competency relating to e-learning instructional designer was analyzed. Second, based on the items of information from this analysis, selection and validity verification took place with 5 e-learning specialists group. Third, the opinion of experts who were in charge of hiring in e-learning companies were collated with the questionnaire. Lastly, the human cloud platform framework was proposed based on opinion results. Results - The framework was comprised of 7 domains and 27 items in order to develop the human cloud platform for e-learning instructional designer. The analysis results showed that the most highly considered item were 'skill (4.60)' that employee already have the capability. Following this (in order) were 'project type (4.56)', 'work competency (4.56)', and 'strength area of instructional design (4.52)'. Conclusions - The 27 items in the human cloud platform framework were suggested in this study. Following this, we can consider to develop the human cloud platform for finding a job and hiring e-learning instructional designer easily. For successful platform operation, we need to consider reliability between employer and employee. In addition, we need quality assurance system based on operation has public confidence.