• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.5
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• pp.520-530
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• 2016

Since FDD massive MIMO (multiple-input multiple-output) system deploys hundreds of transmit antennas at base station (BS) compared to conventional MIMO system, the overhead of transmitting channel state information reference signal (CSI-RS) increases proportionally to the number of transmit-antennas. To overcome these disadvantages, we proposed beamforming based CSI-RS transmission technique for FDD massive MIMO system which transmit CSI-RS by limited amount of downlink resources.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.49 no.7
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• pp.345-349
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• 2000

This paper presents an extended integral control with the PI controller by introducing the delay and decaying factors. The extended integral control scheme is developed by substituting the proportional convolution integral control for the PI(Proportional Integral) control. So far, the integral part of PI controller produces a signal that is proportional to the time integral of the input signal to the controller. The steady-state operation points are affected forever by errors in the past due to the input signal containing the information of the error in the past. These phenomena may cause some disturbances for other control purposes related to the given PI control. Introduction of forgetting factors to the error in the past can resolve the disturbance problems. Various forgetting factors are developed using the delay elements, the decaying factors, and the combination of the delay and decaying factors. The proposed various extended integral control schemes can be applicable to the corresponding PI control designs in which the error in the past may badly affect the current steady-state operation points and may cause some disturbances for other control purposes.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.101-104
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• 2001

In this paper, we propose the Digital Automatic Gain Controller for IEEE 802.11a High-speed Physical Layer in the 5 GHz Band. The input gain is estimated by calculating the energy of the training symbol that is a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Journal of the Institute of Convergence Signal Processing
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• v.2 no.4
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• pp.71-76
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• 2001

In this paper we propose the Digital Automatic Gain Controller for IEEE 802.11a-High-speed Physical Layer in the 5 GHz Band. The input gain it estimated by calculating the energy of the training symbol that it a synchronizing signal. The renewal gain is calculated by comparing the estimated gain with the ideal gain. The renewal gain is converted into the controlled voltage for GCA to reduce or amplify the input signals. We used a piecewise-linear approximation to reduce the hardware size. The gain control is performed seven times to provide more accurate gain control. The proposed automatic gain controller is designed with VHDL and verified by using the Xilinx FPGA.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.4
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• pp.293-296
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• 2007

In this paper, we propose the systolic array architecture for the vector median filter. In the color image processing, the vector signal (i.e. the color) consists of three elements, red, green and blue. The vector median filter is very effective to utilize the correlation among red, green and blue elements. The computational complexity of the proposed architecture for computing the vector median of N vector signals is (N+2) clock periods compared to the (3N+1) clock periods in the previous method. In addition to, the input vector signals can be loaded in serial in the proposed architecture. In the previous method, N input vector signals should be loaded to the vector median filter in parallel at the first clock. The proposed architecture is implemented with FPGA.

• Proceedings of the KSR Conference
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• 2008.06a
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• pp.691-706
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• 2008

ATP(Automatic Train Protection) system in railway signaling system is the important one grasping the position and velocity of a train. The wayside transmitter of ATP system is installed between rails. In concrete slab track, the signal current using wayside transmitter of ATP system is influenced by reinforcing bars. The magnetic coupling between reinforcing bars and wayside transmitter of ATP system as a filter makes an input current distorted. So, it makes an alternating current signal with a desirable size not transmit to on-board system of a train. Way to decrease the distortion of an input current signal frequency is to avoid maximum induction current frequency. And the induction phenomenon between reinforcing bars insulated and wayside transmitter of ATP system does not occur. In this paper, we represent the model about wayside transmitter of ATP system and reinforcing bars on the concrete slab tracks, and calculated the parameters demanded for the model. Also, we demonstrated it through the Maxwell program. Furthermore, we calculated impedance on wayside transmitter used in KVB system and ERTMS/ETCS system which are a kind of ATP system, frequency response of induction current, using the Matlab, and demonstrated the validity of it, using the PSpice program.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.276-281
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• 2005

This paper presents a low voltage operating IF QPSK receiver block which is consisted of programmable gain amplifier (PGA) and analog to digital converter. This PGA has 6 bit control and 250MHz bandwidth, $0{\sim}20\;dB$ gain range. Using the proposed PGA architecture (low distortion gain control switch block), we can process the continuous fully differential $0.2{\sim}2.5Vpp$ input/output range and 44MHz carrier with 2 MHz bandwidth signal at 1.8V supply voltage. Using the sub-sampling technique (input freq. is $44{\sim}46MHz$, sampling freq. is 25MHz), we can process the IF QPSK signal ($44{\sim}46MHz$) which is the output of the 6 bit PGA. We can get the SNDR 35dB, which is the result of PGA and ADC at full gain mode. We fabricated the PGA and ADC and the digital signal processing block of the IF QPSK with the 0.18um CMOS MIM process 1.8V Supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.16 no.12
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• pp.1219-1228
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• 1991

In the actual case, a model of noise canceller using adaptive filter has both a channel transfer function from noise source to main signal input and to noise canceller input. The previous models of noise canceller have been considered to be only one side channel transfer function. Therefore, it is proposed that a new model has two channel transfer functions and derives an optimal tranfer function of adaptive noise canceller. The adaptive filter is using the joint process lattice filter that has fast adaptive speed. The signal noise radio has been improved by a model of ANC-ALE and it is confirmed with computer simulation. Beside, a dc bias is very effective for noise cancelling, especially to the particular signal.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.209-212
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• 2003

In this paper, we have analyzed a multiwavelet filter bank architecture which have several bases. The filter bank composed of multiwavelets bases is matrix-valued. Multiwavelets offer simultaneous orthogonality, symmetry, and short support, which is not possible for the scalar wavelet system, hence multiwavelet system can obtain excellent performance in signal analysis and compress. Also the multiwavelet differs from the scalar wavelet system in requiring two or more input streams to the multiwavelet filter bank. In this paper, we describe methods for obtaining such a input stream and how apply the actual data.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.