• 제목/요약/키워드: Input queuing

검색결과 23건 처리시간 0.026초

Queuing을 이용한 UDP 설계 알고리즘과 데이터그램 분석 (Design Algorithm & Datagram Analysis of UDP using Queuing)

  • 엄금용
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
    • /
    • pp.231-233
    • /
    • 2004
  • Queuing is waiting lines which play routing service when packet entered. Queuing is decide how and whom is going to provide priority service. This is kind of first in first out(FIFO) or weighted fair queuing(WFQ) method. In this study, UDP design using WFQ way to serve to provide service evenly and rapidly in network. Also in actuality internet, datagram analyzed by packet captured. Queuing services through the requesting port number, input, output, output queuing creation & delete, message request by internet control message protocol(ICMP). Queuing designed in control block module, input queues, input/output module composition. In conclusion, I have confirm queuing result of WFQ method by the datagram information analyzed.

  • PDF

MIN(Multistage Interconnection Networks)망을 이용한 가상 입력 버퍼 반얀 스위치 설계 (A Virtual Partially Shared Input-Buffered Banyan Switch Based on Multistage Interconnection Networks)

  • 권영호;김문기;이병호
    • 한국정보과학회:학술대회논문집
    • /
    • 한국정보과학회 2004년도 가을 학술발표논문집 Vol.31 No.2 (3)
    • /
    • pp.301-303
    • /
    • 2004
  • 현재 ATM 망에서 다양한 형태의 스위치 구조가 제안 되었으며 스위치 구조는 크게blocking 과 nonblocking 스위치로 나눌 수 있다. nonblocking 스위치는 버퍼의 위치에 따라 input queuing, output queuing, shared buffer switch로 나뉘며 그 중에 입력 버퍼형은 하드웨어 구현이 쉬운 장점이 있으나 HOL블로킹으로 인하여 처리 효율이 낮다는 단점이 있다. 본 논문에서는 이러한 입력 버퍼형 ATM 교환기의 문제점을 해결하기 위하여 가상적인 입력버퍼와 MUX를 이용한 입력버퍼형 반얀 스위치 모델을 제안한다.

  • PDF

Analysis of Distributed DDQ for QoS Router

  • Kim, Ki-Cheon
    • ETRI Journal
    • /
    • 제28권1호
    • /
    • pp.31-44
    • /
    • 2006
  • In a packet switching network, congestion is unavoidable and affects the quality of real-time traffic with such problems as delay and packet loss. Packet fair queuing (PFQ) algorithms are well-known solutions for quality-of-service (QoS) guarantee by packet scheduling. Our approach is different from previous algorithms in that it uses hardware time achieved by sampling a counter triggered by a periodic clock signal. This clock signal can be provided to all the modules of a routing system to get synchronization. In this architecture, a variant of the PFQ algorithm, called digitized delay queuing (DDQ), can be distributed on many line interface modules. We derive the delay bounds in a single processor system and in a distributed architecture. The definition of traffic contribution improves the simplicity of the mathematical models. The effect of different time between modules in a distributed architecture is the key idea for understanding the delay behavior of a routing system. The number of bins required for the DDQ algorithm is also derived to make the system configuration clear. The analytical models developed in this paper form the basis of improvement and application to a combined input and output queuing (CIOQ) router architecture for a higher speed QoS network.

  • PDF

Comparative Performance Analysis of Network Security Accelerator based on Queuing System

  • Yun Yeonsang;Lee Seonyoung;Han Seonkyoung;Kim Youngdae;You Younggap
    • 대한전자공학회:학술대회논문집
    • /
    • 대한전자공학회 2004년도 ICEIC The International Conference on Electronics Informations and Communications
    • /
    • pp.269-273
    • /
    • 2004
  • This paper presents a comparative performance analysis of a network accelerator model based on M/M/l queuing system. It assumes the Poisson distribution as its input traffic load. The decoding delay is employed as a performance analysis measure. Simulation results based on the proposed model show only $15\%$ differences with respect to actual measurements on field traffic for BCM5820 accelerator device. The performance analysis model provides with reasonable hardware structure of network servers, and can be used to span design spaces statistically.

  • PDF

다수의 이질적 IBP/D/1큐잉 모형의 분석을 위한 근사 알고리즘 (An Approximate algorithm for the analysis of the n heterogeneous IBP/D/l queuing model)

  • 홍석원
    • 한국정보통신학회논문지
    • /
    • 제4권3호
    • /
    • pp.549-555
    • /
    • 2000
  • 본 논문에서는 n개의 버스트 입력 트래픽을 처리하는 이산 시간 큐잉 모형을 분석하기 위한 근사 계산 알고리즘을 제안한다. 입력되는 각각의 버스트 트래픽은 IBP(Interrupted Bernoulli Process)로 모형화된다. 이 알고리즘은 n 개의 입력 프로세스를 하나의 상태 변수로 표시하여 n 개의 입력 프로세스로 표현된 마코프 체인(Markov Chain)의 확률 전이 상태를 단순화한다. 이렇게 단순화된 하나의 상태 변수를 이용하여 큐잉모형의 상태 전이를 표현하고 이를 완전 수치 계산에 의해 해를 구한다. 이러한 절차를 통해 구한 큐 길이, 대기 시간 분포를 시뮬레이션에 의해 구한 값과 비교하여 알고리즘의 타당성을 검증한다.

  • PDF

구조안전진단에서의 3D 레이저 스캐너 투입 성과 분석 (Analysis of 3D Laser Scanner Input Performance in Structual Safety Diagnosis)

  • 성도윤;백인수;김재준;함남혁
    • 한국BIM학회 논문집
    • /
    • 제11권3호
    • /
    • pp.34-44
    • /
    • 2021
  • This study quantitatively analyzes the work performance of the structural safety diagnosis team that diagnoses pipe racks. To this end, a method for evaluating the performance of the structural safety diagnosis team using the queuing model was proposed. For verification, the case of applying the existing method and the method of introducing a 3D laser scanner for one site was used. The period, number of people, and initial investment cost of each project were collected through interviews with case project experts. As a result of analyzing the performance of the structural safety diagnosis team using the queuing model, it was possible to confirm the probability of delay in the work of each project and the amount of delayed work. Through this, the cost (standby cost) when the project was delayed was analyzed. Finally, economic analysis was conducted in consideration of the waiting cost, labor cost, and initial investment cost. The results of this study can be used to decide whether to introduce 3D laser scanners.

입력큐 교환기에서의 우선순위 파이프라인 순환 스케줄링 (Pipelined and Prioritized Round Robin Scheduling in an Input Queueing Switch)

  • 이상호;신동렬
    • 대한전기학회논문지:시스템및제어부문D
    • /
    • 제52권6호
    • /
    • pp.365-371
    • /
    • 2003
  • Input queued switch is useful for high bandwidth switches and routers because of lower complexity and fewer circuits than output queued. The input queued switch, however, suffers the HOL-Blocking, which limits its throughput to 58%. To overcome HOL-Blocking problem, many input-queued switch controlled by a scheduling algorithm. Most scheduling algorithms are implemented based on a centralized scheduler which restrict the design of the switch architecture. In this paper, we propose a simple scheduler called Pipelined Round Robin (PRR) which is intrinsically distributed by each input port. We presents to show the effectiveness of the proposed scheduler.

오픈 큐잉 네트워크 모델을 이용한 가상회선 서비스 성능 분석 (Performance Analysis of Virtual Circuit Services Using Open Queuing Network Models)

  • 조용구;오영환
    • 한국통신학회논문지
    • /
    • 제17권3호
    • /
    • pp.225-231
    • /
    • 1992
  • In this paper, queuing networks with open chains are considerd to analyze the performance of packet switching networks. Networks are classified into backbone and local access networks. Networks for performance analysis are distributed to twelve regions and DNS is the backbone. Analysis was conducted using the real values from the input to existing networks and mathematical estimation values. As the result of analysis, the mean of end-to-and delay for each chain was presented. Except special regions, we found that there was a little difference between real values and mathematical estimation values. However, there could be a performance problem in total networks due to the increase of communication volumes in each region. So we proposed some solutions to this problem.

  • PDF

Grant-Aware Scheduling Algorithm for VOQ-Based Input-Buffered Packet Switches

  • Han, Kyeong-Eun;Song, Jongtae;Kim, Dae-Ub;Youn, JiWook;Park, Chansung;Kim, Kwangjoon
    • ETRI Journal
    • /
    • 제40권3호
    • /
    • pp.337-346
    • /
    • 2018
  • In this paper, we propose a grant-aware (GA) scheduling algorithm that can provide higher throughput and lower latency than a conventional dual round-robin matching (DRRM) method. In our proposed GA algorithm, when an output receives requests from different inputs, the output not only sends a grant to the selected input, but also sends a grant indicator to all the other inputs to share the grant information. This allows the inputs to skip the granted outputs in their input arbiters in the next iteration. Simulation results using OPNET show that the proposed algorithm provides a maximum 3% higher throughput with approximately 31% less queuing delay than DRRM.

중재 지연 내성을 가지는 입력 큐 스위치의 다중 큐 관리기 구조 (Architecture of Multiple-Queue Manager for Input-Queued Switch Tolerating Arbitration Latency)

  • 정갑중;이범철
    • 한국통신학회논문지
    • /
    • 제26권12C호
    • /
    • pp.261-267
    • /
    • 2001
  • 본 논문은 입력 버퍼와 중앙 중재기 사이에 중재 정보 전달 지연을 갖는 고속 셀/패킷 스위치에 적용된 다중 입력 큐 관리기의 구조 및 Chip 설계 기법을 제안한다. 제안된 다중 입력 큐 관리기의 구조는 wire-speed 셀/패킷 라우팅을 지원하고 입력 버퍼와 중앙 중재기 사이의 중재 정보 전송 지연에 대한 내성을 지원한다. 고속 쉬프터를 사용한 새로운 요청 신호 관리 방법을 사용하여 중재 정보 전송 지연에 대처하며 그로 인한 전체 스위치의 성능 향상을 제공한다. 제안된 다중 입력 큐 관리기는 FPGA Chip을 이용하여 구현되었으며 포트 당 OC-48c 속도를 지원한다. 본 다중 입력 큐 관리기를 이용하여 16$\times$16 스위치 크기와 입력 포트 당 128 셀 공유 버퍼를 가지는 입력 큐 스위치 시스템에서 최대 98.6%의 성능을 가지는 400bps의 스위치 시스템을 개발하였다.

  • PDF