• Journal of the Korean Society of Safety
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• v.27 no.3
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• pp.57-62
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• 2012

The purpose of this paper is to find dangerous factors of a water purifier when water leaks due to inappropriate use and analyze the patterns of damaged parts in order to provide data for the examination of the cause of the problem. If the water purifier is inspected and managed by a non-specialist, when the FLC(Float Level Controller) at the top is inclined, water leakage may occur to the water purifier. The leaked water flows onto the cables and hoses and enters the thermostat terminal, heater, PCB, power supply connection connector, etc., becoming a dangerous factor that may cause a system failure, fire, etc. Due to the water that entered the input terminal, low noise and white smoke were generated at first. However, the flame gradually propagated due to the continuous inflow of moisture. It was found that when moisture reached the PCB, a carbonized conductive path was formed at the varistor terminal, input terminal, semiconductor device terminal, etc., and the flame became larger, which might result in a fire. From the metal microscope analysis of a damaged condenser terminal, it was found that the amorphous structure unique to copper cable disappeared, and voids, boundary surface and disorderly fine particles occurred. Also, in the case of the connector into which moisture penetrated, fusion and deformation occurred at the cable connection clips. The result of analysis of the power supply cable connector using a thermal image camera showed that most of the heat was generated from the cable connection clips and the temperature at the connection center was normal.

• Korean Journal of Agricultural Science
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• v.23 no.2
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• pp.272-284
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• 1996

The present study has quantitatively assessed the regional production, income and employment impact resulting from the construction and operation of nuclear power plant (NPP) upon the domestic local areas by applying the regional input-output analysis model to the case of Wolsong unit-l site. The conclusions regarding the most likely regional economic impacts upon the wolsong site are summarized as follows: 1. The income multipliers are calculated to be 1.563 for the construction phase and 1.500 for the operation phase. These values are relatively high compared with those of other conventional facilities. 2. The level of total employee's wage induced employment associated with the construction phase has been estimated to be 37,000 while that with the operational phase in 1990 to be 5,610. 3. With relation to the aspect of resident welfare it is found that the industrial sector associated with electricity, gas and water supply have remarkably improved with the construction of the NPP. 4. The NPP siting has induced substantial changes in interindustry (input-output) structures of the Wolsong unit-l site which is one of the rural areas where all the domestic NPPs are sited. Such changes are attributed to the industrial recomposition of the region. 5. With the application of other regional economic analysis models and the use of more sufficient regional data, other detailed studies on the economic impact analysis of domestic NPP-related facility sitings are suggested to be carried out further since the influence of NPP sitings is significant to the national economic impact as well as the regional economic impact.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.5
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• pp.1-12
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• 1999

A new algorithm of constructing binary decision diagram(BDD) for design verification of switch-level circuits is proposed in this paper. In the switch-level circuit, functions are characterized by serial and parallel connections of switches and the final logic values may have high-impedance and unstable states in addition to the logic values of 0 and 1. We extend the BDD to represent functions of switch-level circuits as acyclic graphs so called switch-level binary decision diagram (SLBDD). The function representation of the graph is in the worst case, exponential to the number of inputs. Thus, the ordering of decision variables plays a major role in graph sizes. Under the existence of pass-transistors and domino-logic of precharging circuitry, we also propose an input ordering algorithm for the efficiency in graph sizes. We conducted several experiments on various benchmark circuits and the results show that our algorithm is efficient enough to apply to functional simulation, power estimation, and fault-simulation of switch-level design.

• Journal of the Earthquake Engineering Society of Korea
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• v.15 no.6
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• pp.11-18
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• 2011

Accurate modal identification analysis is required to reasonably perform a seismic qualification of safety-related electric equipment installed in nuclear power plants (NPPs). This study evaluates a variation of the modal properties of an electric equipment cabinet structure in NPPs according to the excitation levels. For the study, an actual electric equipment cabinet was selected as a specimen and was dynamically tested by using a portable exciter in accordance with the level of input vibration energy. Tests were classified into two sets: with-door cases, and without-door cases. Frequency response functions were computed from the signals of the acceleration responses and input motions measured from the vibration tests. A polynomial curve fitting algorithm was used to extract the modal properties from the frequency response functions. This study reviews the variation of the modal properties according to the variation of the excitation levels. The results of the study show that the modal frequencies and the modal dampings of the object specimen varies nonlinearly according to the excitation level of the test motion. Attaching the door increases the modal damping of the cabinet.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 2022.06a
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• pp.339-343
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• 2022

In this study, a method for simplifying the structure of the VDES RF receiver, and the gain control method of the receiver to comply with the international standard in this structure was described. The input level of the wanted signal and unwanted signal to the receiver was defined, and when the two signals were input, the saturation state at the ADC was checked at the receiver output. As a result of the simulation by the circuit simulator, it was satisfied that the output power of the receiver was in the SFDR region of ADC with respect to the adjacent channel interference ratio, intermodulation, and blocking level. Through this study, it was found that the structure of th proposed RF receiver conforms to the international standard.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.1075-1080
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• 2015

A hybrid electric vehicle (HEV) powertrain has more than one energy source including a high-voltage electric battery. However, for a high voltage electric battery, the average current is relatively low for a given power level. Introduced to increase the voltage of a HEV battery, a compact, high-efficiency boost converter, sometimes called a step-up converter, is a dc-dc converter with an output voltage greater than its input voltage. The inductor occupies more than 30% of the total converter volume making it difficult to get high power density. The inductor should have the characteristics of good thermal stability, low weight, low losses and low EMI. In this paper, Mega Flux^® was selected as the core material among potential core candidates. Different structured inductors with Mega Flux^® were fabricated to compare the performance between the conventional air cooled and proposed potting structure. The proposed inductor has reduced the weight by 75% from 8.8kg to 2.18kg and the power density was increased from 15.6W/cc to 56.4W/cc compared with conventional inductor. To optimize the performance of proposed inductor, the potting materials with various thermal conductivities were investigated. Silicone with alumina was chosen as potting materials due to the high thermo-stable properties. The proposed inductors used potting material with thermal conductivities of 0.7W/m·K, 1.0W/m·K and 1.6W/m·K to analyze the thermal performance. Simulations of the proposed inductor were fulfilled in terms of magnetic flux saturation, leakage flux and temperature rise. The temperature rise and power efficiency were measured with the 40kW boost converter. Experimental results show that the proposed inductor reached the temperature saturation of 107℃ in 20 minutes. On the other hand, the temperature of conventional inductor rose by 138℃ without saturation. And the effect of thermal conductivity was verified as the highest thermal conductivity of potting materials leads to the lowest temperature saturations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.10
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• pp.52-62
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• 2003

This paper discusses ternary logic gate, ternary D flip-flop, and ternary four-digit parallel input/output register. The ternary logic gates consist of n-channel pass transistors and neuron MOS(νMOS) threshold inverters on voltage mode. They are designed with a transmission function using threshold inverter that are in turn, designed using Down Literal Circuit(DLC) that has various threshold voltages. The νMOS pass transistor is very suitable gate to the multiple-valued logic(MVL) and has the input signal of the multi-level νMOS threshold inverter. The ternary D flip-flop uses the storage element of the ternary data. The ternary four-digit parallel input/output register consists of four ternary D flip-flops which can temporarily store four-digit ternary data. In this paper, these circuits use 3.3V low power supply voltage and 0.35m process parameter, and also represent HSPICE simulation result.

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.

• Clean Technology
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• v.23 no.3
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• pp.248-255
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• 2017

In dismantling factories for recycling, it is important to input actual working data to a personal computer (PC) in order to monitor the work results and related recycling rate of the inputs. This should be performed with a keyboard, a mouse, or other devices. But when a worker is working in the factory, it could be bothersome or time consuming to go to the PC. Especially, workers who works at dismantling factories have a generally low education level are scared to use a PC, which could be used as a pretext for not using the PC. In some cases, data input is performed by a worker after the day's job. In this case, it could take additional time, the worker can make more mistakes, and the data could be unreliable. In this study, we developed a man-machine interface (MMI) device using a safety helmet. A joystick-like device, pushbuttons, and a radio frequency (RF) device for wireless communication is equipped in a safety helmet. This MMI device has functions similar to a PC mouse, and it has a long communication distance. RF is used because it consumes less battery power than Bluetooth. With this MMI device, workers need not go to a PC to input data or to control the PC, and they can control the PC from a long distance. The efficiency of PCs in a factory could be increased by using the developed MMI system, and workers at the dismantling factories could have less reluctance in using the PC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.8
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• pp.1464-1474
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• 1994

GPS(Global Positioning System)is a satellite-based navigation system that we can survey where we are, anywhere and anytime. In this paper, delay-lock loop of the receiver which detects the navigation data is theoretically analyzed, and designed using the digital logic circuit. Also logic operations for the synchronization are analyzed. The designed system consists of the correlator which correlates the received C/A code and the generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock syntheizer which generates the clock of the C/A code generator to control the C/A code phase and clock rate. From the analyses results of the proposed digital delay-lock loop system, the system has the detection propertied over 90% when its input signal power is above-113.98dB. The influence of input signal variation of digital delay loop, which is the input of A/D converter, is investigated and the performance is analyzed with the variation of threshold level via the computer simulation. The logic simulation results show that the designed system detects precisely the GPS navigation data.