• Journal of Sensor Science and Technology
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• v.32 no.2
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• pp.105-109
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• 2023

In this study, we present a power-efficient driving method for gas sensor systems based on the analysis of input signal characteristics. The analysis of the gas sensor output signal characteristics in the frequency domain shows that most of the signal portions are distributed in a relatively low frequency region when extracting the gas sensor signal, which can lead to further performance improvement of the gas sensor system. Therefore, the proposed gas signal extracting technique changes the operating frequency of the read-out circuit based on the frequency characteristics of the output signal of the gas sensor, resulting in a reduction of power consumption at the whole system level. The proposed sensing technique, which can be applied to a general-purpose commercial gas sensor system, was implemented in a printed circuit board (PCB) to verify its effectiveness at the commercial level.

• ETRI Journal
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• v.31 no.5
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• pp.598-600
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• 2009

A highly efficient and compactly integrated balanced power amplifier (PA) for W-CDMA handset applications is presented. To overcome the size limit of a typical balanced PA, a bulky input divider is integrated into a PA MMIC, and a complex output network is replaced with simple lumped-element networks. For efficiency improvement at the low output power level, one of the two amplifiers in parallel is deactivated and the other is partially operated with corresponding load impedance optimization. The implemented PA shows excellent average current consumption of 34.5 mA in urban and 56.3 mA in suburban environments, while exhibiting very good load-insensitivity under condition of VSWR=4:1.

• Proceedings of the KIEE Conference
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• 1990.11a
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• pp.340-343
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• 1990

Recently, Power Electronics system increase makes harmonics and low input power factor problem. In this paper present new analysis method of PWM Boost AC/DC Converter. This PWM AC/DC Converter is capability of unity power factor, control of DC side voltage level, generation, and near sinusoidal current in 3-phase line. The control of this type of converter is widely discussed. And this paper propose new phase convert function and analysis in steady state of system to obtain amplitude and phaser of switching function. This switching function is general solution and it can use in high power approach. And this control method show the clear meaning of control variable. This paper propose new analysis method of Boost AC/DC Converter of steady state and 3-phase 2KW experimental system show its validity.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2065-2069
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• 2014

The DAC-7512E is a 12-bit digital to analog converter that is low power and a single package with internal buffers. The DAC-7512E takes up minimal PCB area for applications of space power electronics design. The spacecraft mass is a crucial point considering spacecraft launch into space. Therefore, we have performed a TID test for the DAC-7512E 12-bit serial input digital to analog converter to reduce the spacecraft mass by using a low-level Gamma-ray irradiator with $Co^{60}$ gamma-ray sources. The irradiation with $Co^{60}$ gamma-rays was carried out at doses from 0 krad to 100 krad to check the error status of the device in terms of current, voltage and bit error status during conversion. The DAC-7512E 12-bit serial digital to analog converter should work properly from 0 krad to 30 krad without any error.

• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.45-48
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• 2004

To improve the efficiency characteristics in the resonant converter using the contact-less power supply with the large air-gap and the long primary winding, this paper suggests the three-level series-parallel resonant converter(SPRC). The voltage gain characteristics of the proposed converter have the unit gain in a resonance frequency point of the series and parallel, and input voltage and current in the primary of SPRC are always In phase for the all equivalent load resistance because of the parallel resonant tank of the high impedance. The results are verified on the simulation based on the theoretical analysis and the 4kW experimental prototype.

• Journal of Power Electronics
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• v.16 no.3
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• pp.960-969
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• 2016

High-power three-level voltage-source converters are widely utilized in high-performance AC drive systems. In several ultra-power instances, the harmonics on the grid side should be reduced through multiple rectifications. A combined harmonic elimination method that includes a dual primary-side series-connected winding transformer and selective harmonic elimination pulse-width modulation is proposed to eliminate low-order current harmonics on the primary and secondary sides of transformers. Through an analysis of the harmonic influence caused by dead time and DC magnetic bias, a synthetic compensation control strategy is presented to minimize the grid-side harmonics in the dual primary side series-connected winding transformer application. Both simulation and experimental results demonstrate that the proposed control strategy can significantly reduce the converter input current harmonics and eliminates the DC magnetic bias in the transformer.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.1
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• pp.52-56
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• 2014

In this paper, a high-efficiency power amplifier is implemented using a gate and drain bias control circuit for WPT (Wireless Power Transmission). This control circuit has been employed to improve the PAE (Power Added Efficiency). The gate and drain bias control circuits consists of a directional coupler, power detector, and operation amplifier. A high gain two-stage amplifier using a drive amplifier is used for the low input stage of the power amplifier. The proposed power amplifier that uses a gate and drain bias control circuit can have high efficiency at a low and high power level. The PAE has been improved up to 80.5%.

• Journal of Power Electronics
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• v.18 no.2
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• pp.432-444
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• 2018

This paper presents a capacitor voltage balancing topology using a three-level boost converter (TLBC) for a neutral point clamped (NPC) three-level inverter fed surface permanent magnet synchronous motor drive (SPMSM). It enhanced the performance of the drive in terms of its voltage THD and torque pulsation. The main attracting feature of the proposed control is the boosting of the input voltage and at the same time the balancing of the capacitor voltages. This control also reduces the computational complexity. For the purpose of close loop vector control, a software based cost effective resolver to digital converter RDC-less estimation is implemented to calculate the speed and position. The proposed drive is simulated in the MATLAB/SIMULINK environment and an experimental investigation using dSPACE DS1104 validates the proposed drive system at different operating condition.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.5
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• pp.385-393
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• 2020

This study introduces an analysis and control method for the variation of neutral point current in a grid-tied three-level neutral point clamped (NPC) converter under various grid imbalance operating conditions. Various fault cases with unbalanced amplitude and phase are systematically categorized and described using a unified metric called the imbalance factor. The fundamental component of neutral point current is generated under grid imbalance cases. The pattern and behavior of this fundamental component of neutral point current highly depend on the imbalance factor regardless of the particular type of grid fault cases. The control scheme for regulating the negative sequential component of AC input current effectively reduces the size of the fundamental component of neutral point current under a wide range of grid imbalance cases. The control scheme will enable a grid-tied three-level NPC converter to operate reliably and stably under various types of grid faults.

• The Journal of the Korea Contents Association
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• v.6 no.3
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• pp.38-45
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• 2006

A dual-level low voltage differential signalling (DLVDS) circuit is proposed aiming at reducing transmission lines for a LCD driver IC. We apply two data to the proposed DLVDS circuit as inputs. Then, the transmitter converts two inputs to two kinds of fully differential signals. In this circuit, two transmission lines are sufficient to transfer two inputs while keeping the LVDS feature. However, the circuit has a common mode bias fluctuation due to difference of the input bias and the reference bias. We compensate the common mode bias fluctuation using a feedback circuit of the current source bias. The receiver recovers the original input data through a level decoding circuit. We fabricated the proposed circuit using $0.25{\mu}m$ CMOS technology. The simulation results of proposed circuit shows 1-Gbps/2-line data rate and 35mW power consumption at 2.5V supply voltage, respectively.