• Title/Summary/Keyword: Input power level

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Logic gate implementation of constant amplitude coded CS/CDMA transmitter (정포락선 부호화된 CS-CDMA 송신기의 논리 게이트를 이용한 구현)

  • 김성필;류형직;김명진;오종갑
    • Proceedings of the IEEK Conference
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    • 2003.11c
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    • pp.281-284
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    • 2003
  • Multi-code CDMA is an appropriate scheme for transmitting high rate data. However, dynamic range of the signal is large, and power amplifier with good linearity is required. Code select CDMA (CS/CDMA) is a variation of multi-code CDMA scheme that ensures constant amplitude transmission. In CS/CDMA input data selects multiple orthogonal codes, and sum of these selected codes are MPSK modulated to convert multi-level symbol into different carrier phases. CS/CDMA system employs level clipping to limit the number of levels at the output symbol to avoid hish density of signal constellation. In our previous work we showed that by encoding input data of CS/CDMA amplitude of the output symbol can be made constant. With this coding scheme, level clipping is not necessary and the output signal can be BPSK modulated for transmission. In this paper we show that the constant amplitude coded(CA-) CS/CDMA transmitter can be implemented using only logic gates, and the hardware complexity is very low. In the proposed transmitter architecture there is no apparent redundant encoder block which plays a major role in the constant amplitude coded CS/CDMA.

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Design and Fabrication of a S-BAND Receiver for Low Orbit Satellite (저궤도 위성용 S-BAND 수신기 설계 및 제작)

  • Choi, Young-Jin
    • Proceedings of the IEEK Conference
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    • 2005.11a
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    • pp.35-38
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    • 2005
  • In this study, S-Band receiver for low orbit satellite is implemented. The developed receiver is double super-heterodyne type and STDN compatible. Input/output frequency of receiver is 2034.747MHz and 18.414MHz used for KOMPSAT 2 satellite. Overall gain(@AGC=0V) and image rejection were 92.4dB and 50.2dB respectively. It was verified that receiver has stable performance to the temperature limit, power supply voltage variation and input signal level range.

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A Single Phase Multi-level Active Power Filter System using Instantaneous Reactive Power Harmonic Detection Method (순시 무효 전력 고조파 검출방법을 이용한 단상 멀티레벨 능동전력 필터)

  • Kim Soo-Hong;Kim Sung-Min;Lee Kang-Hee;Kim Yoon-Ho
    • The Transactions of the Korean Institute of Power Electronics
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    • v.10 no.3
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    • pp.296-301
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    • 2005
  • This paper proposing the use of the Instantaneous reactive power method as a harmonic detection method for a single phase active filter system. This method is to detect harmonic components through d-q frame approach. The conventional use of d-q frame approach for a 3-phase system Is extended to the single phase system. The proposed system uses a multi-level inverter for harmonic compensation and the inverter is connected to the input side without using transformers. The proposed algorithm is verified by simulation and experiment.

Adaptive second-order nonsingular terminal sliding mode power-level control for nuclear power plants

  • Hui, Jiuwu;Yuan, Jingqi
    • Nuclear Engineering and Technology
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    • v.54 no.5
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    • pp.1644-1651
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    • 2022
  • This paper focuses on the power-level control of nuclear power plants (NPPs) in the presence of lumped disturbances. An adaptive second-order nonsingular terminal sliding mode control (ASONTSMC) scheme is proposed by resorting to the second-order nonsingular terminal sliding mode. The pre-existing mathematical model of the nuclear reactor system is firstly described based on point-reactor kinetics equations with six delayed neutron groups. Then, a second-order sliding mode control approach is proposed by integrating a proportional-derivative sliding mode (PDSM) manifold with a nonsingular terminal sliding mode (NTSM) manifold. An adaptive mechanism is designed to estimate the unknown upper bound of a lumped uncertain term that is composed of lumped disturbances and system states real-timely. The estimated values are then added to the controller, resulting in the control system capable of compensating the adverse effects of the lumped disturbances efficiently. Since the sign function is contained in the first time derivative of the real control law, the continuous input signal is obtained after integration so that the chattering effects of the conventional sliding mode control are suppressed. The robust stability of the overall control system is demonstrated through Lyapunov stability theory. Finally, the proposed control scheme is validated through simulations and comparisons with a proportional-integral-derivative (PID) controller, a super twisting sliding mode controller (STSMC), and a disturbance observer-based adaptive sliding mode controller (DO-ASMC).

A Study on the Level Control in the Steam Generator of a Nuclear Power Plant by using Model Predictive Controller (MPC를 이용한 원전 증기발생기의 수위제어에 관한 기초연구)

  • Son, Duk-Hyun;Lee, Chang-Goo;Han, Jin-Wook;Han, Hu-Suk
    • Proceedings of the KIEE Conference
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    • 2000.07d
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    • pp.2495-2497
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    • 2000
  • Level control in the steam generator of a nuclear power plant is important process. But, the low power operation of nuclear power plant causes nonlinear characteristics and non minimum phase characteristics (swell and shrink), change of delay. So, we can't lead good results with conventional PID controller. Particularly, the design of controller with constraints is necessary. This paper introduces MPC(Model Predictive Control) with constraints and designs a good performance MPC controller in spite of the input constraints and nonlinear characteristics, non-minimum phase characteristics

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Analysis, Design and Implementation of a Soft Switching DC/DC Converter

  • Lin, Bor-Ren
    • Journal of Power Electronics
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    • v.13 no.1
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    • pp.20-30
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    • 2013
  • This paper presents a soft switching DC/DC converter for high voltage application. The interleaved pulse-width modulation (PWM) scheme is used to reduce the ripple current at the output capacitor and the size of output inductors. Two converter cells are connected in series at the high voltage side to reduce the voltage stresses of the active switches. Thus, the voltage stress of each switch is clamped at one half of the input voltage. On the other hand, the output sides of two converter cells are connected in parallel to achieve the load current sharing and reduce the current stress of output inductors. In each converter cell, a half-bridge converter with the asymmetrical PWM scheme is adopted to control power switches and to regulate the output voltage at a desired voltage level. Based on the resonant behavior by the output capacitance of power switches and the transformer leakage inductance, active switches can be turned on at zero voltage switching (ZVS) during the transition interval. Thus, the switching losses of power MOSFETs are reduced. The current doubler rectifier is used at the secondary side to partially cancel ripple current. Therefore, the root-mean-square (rms) current at output capacitor is reduced. The proposed converter can be applied for high input voltage applications such as a three-phase 380V utility system. Finally, experiments based on a laboratory prototype with 960W (24V/40A) rated power are provided to demonstrate the performance of proposed converter.

3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters

  • Seo, Yongho;Cho, Youngkyun;Choi, Seong Gon;Kim, Changwan
    • ETRI Journal
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    • v.36 no.6
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    • pp.924-930
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    • 2014
  • This paper presents a $0.13{\mu}m$ CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of -1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.

Comparison of Two Reactive Power Definitions in DFIG Wind Power System under Grid Unbalanced Condition

  • Ha, Daesu;Suh, Yongsug
    • Proceedings of the KIPE Conference
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    • 2014.07a
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    • pp.213-214
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    • 2014
  • This paper compares two instantaneous reactive power definitions in DFIG wind turbine with a back-to-back three-level neutral-point clamped voltage source converter under unbalanced grid conditions. In general, conventional definition of instantaneous reactive power is obtained by taking an imaginary component of complex power. The other definition of instantaneous reactive power can be developed based on a set of voltages lagging the grid input voltages by 90 degree. A complex quantity referred as a quadrature complex power is defined. Proposed definition of instantaneous reactive power is derived by taking a real component of quadrature complex power. The characteristics of two instantaneous reactive power definitions are compared using the ripple-free stator active power control algorithm in DFIG. Instantaneous reactive power definition based on quadrature complex power has a simpler current reference calculation control block. Ripple of instantaneous active and reactive power has the same magnitude unlike in conventional definition under grid unbalance. Comparison results of two instantaneous reactive power definitions are verified through simulation.

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Multilevel Inverter using Two 5-level Inverters Connected in Series (두 대의 5-레벨 인버터의 직렬결합을 이용한 멀티레벨인버터)

  • Choi, Won-Kyun;Kwon, Cheol-Soon;Hong, Un-Taek;Kang, Feel-Soon
    • The Transactions of the Korean Institute of Power Electronics
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    • v.15 no.5
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    • pp.376-380
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    • 2010
  • This paper presents a circuit configuration of multilevel inverter to increase the number of output voltage levels by using conventional 5-level inverters connected in series. Most of all it can maximize the number of output voltage levels by employing input voltage sources, which have the power of five. When it synthesizes the same number of output voltage levels, the proposed inverter can save the number of switching devices compared with the conventional cascaded H-bridge cell inverter. So it can reduce the size, cost, power consumption of the system. We implemented computer-aided simulation and experiments for a 25-level inverter employing two 5-level inverters.

A Wind Turbine Simulator for Doubly-Fed Induction-type Generator with Automatic Operation Mode Change during Wind Speed Variation (가변 풍속시 운전모드 절환을 고려한 이중여자 유도형 풍력발전기의 시뮬레이터)

  • Song, Seung-Ho;Sim, Dong-Joon;Jeong, Byoung-Chang
    • The Transactions of the Korean Institute of Power Electronics
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    • v.11 no.4
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    • pp.349-360
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    • 2006
  • Controller for doubly-fed induction-type wind generation system should be designed with mechanical power on blade. The controller in this paper consists of upper level controller and lower level controller. The upper level controller determines operating modes according to mechanical input power and calculates proper reference values. There are 4 operating modes - minimum speed control, variable torque control, torque limit control and idle mode. The lower level controller performs current regulated PWM control of rotor-side converter and grid-side inverter. A wind turbine simulator is implemented using doubly-fed induction-type generator and DSP based back-to-back converter to verify the performance of designed controller experimentally.