• 한국어정보학회:학술대회논문집
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• 2016.10a
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• pp.300-304
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• 2016

본 논문에서는 한국어 의미역 결정을 순차열 분류 문제(Sequence Labeling Problem)가 아닌 순차열 변환 문제(Sequence-to-Sequence Learning)로 접근하였고, 구문 분석 단계와 자질 설계가 필요 없는 End-to-end 방식으로 연구를 진행하였다. 음절 단위의 RNN Search 모델을 사용하여 음절 단위로 입력된 문장을 의미역이 달린 어절들로 변환하였다. 또한 순차열 변환 문제의 성능을 높이기 위해 연구된 인풋-피딩(Input-feeding) 기술과 카피넷(CopyNet) 기술을 한국어 의미역 결정에 적용하였다. 실험 결과, Korean PropBank 데이터에서 79.42%의 레이블 단위 f1-score, 71.58%의 어절 단위 f1-score를 보였다.

• Journal of Korean Society for Quality Management
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• v.33 no.3
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• pp.135-148
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• 2005

This paper considers a six sigma project for reducing the project costs through project risk management. The project follows a disciplined process of five phases: define, measure, analyze, improve, and control. A risk management process map is used to identify process input and output variables. Seven key process input variables are selected by using C&E diagram and X-Y matrix and finally four vital few input variables are selected by the related statistical analysis. The optimum alternatives of the vital few input variables are obtained by the method of PUGH matrix. The process is running on control plan and we obtained substantial project cost reductions in early stage of the control phase.

• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.761-764
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• 2000

This paper presents a Fuzzy Neural Network (FNN) system to decide whether or not the right information of lanes can be extracted from gray-level images of road scene. The decision of noisy level of input images has been required because much noises usually deteriorates the performance of feature detection based on image processing and lead to erroneous results. As input parameters to FNN, eight noisiness indexes are constructed from a cumulative distribution function (CDF) and proved the indexes being classifiers of images as the good and the bad corrupted by sources of noise by correlation analysis between input images and the indexes. Considering real-time processing and discrimination efficiency, the proposed FNN is structured by eight input parameters, three fuzzy variables and single output. We conduct much experiments and show that our system has comparable performance in terms of false-positive rates.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.1500-1504
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• 2005

This paper proposes the design methodology of genetic algorithm (GA)-based fuzzy Kalman filter for tracking the maneuvering target. The performance of the standard Kalman Filter (SKF) has been degraded because mismatches between the modeled target dynamics and the actual target dynamics. To solve this problem, we use the method to estimate the increment of acceleration by a fuzzy system using the relation between maneuver filter residual and non-maneuvering one. To optimize the fuzzy system, a genetic algorithm (GA) is utilized and this is then tuned by the fuzzy logic correction. Finally, the tracking performance of the proposed method has been compared with those of the input estimation (IE) technique and the intelligent input estimation (IIE) through computer simulations.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.5
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• pp.808-815
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• 1990

This paper treats with the design method for the single loop oversampled Sigma-Delta A/D converter with one delay and the digital integrator. Such an integrator was kgenerated by means of the bilinear transform of the analog integrator. The frequency spectrums of the quantizer and the decimator output signal are evaluated by FFT respectively. With the performance evaluation system, the values of SNR are obtained versus the input sinusoidal signal amplitude, frequency, the oversampling ratio, the DC-input level, the loop gain and the limitting value of the integrator. As compared with existing results, values of SNR versus the input signal amplitude and the oversampling ratio for the suggested system are about 6dB higher then previously reported results respectively. Furthermore, this approach achieves an about 60dB input dynamic range.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.2
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• pp.22-28
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• 1998

A $g_m$-control technique using a new electronic zener diode (EZD) for CMOS rail-torail input stages is presented. A regulated CMOS inverter is used as an EZD to obtain a constant-$g_m$ input stage. The turn-off characteristic of the proposed EZD is better than that of the existing EZD using two complementarey diodes, and thus, better $g_m$-control can be achieved. With this input stage, a 3V constant-$g_m$ rail-to-rail CMOS op-amp has been designed and fabricated using a $0.8\mu\extrm{m}$single-poly, double-metal CMOS process. Measurements results show that the $g_m$ variation is about 6% over the entire input common-mode range, and the op-amp has a dc gain of 88dB and a unity-gain frequency of 4MHz for $C_L=20pF, R_L=10k\Omega$

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.123-133
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• 1994

This paper presents an output arbitrator for input buffering ATM (Asynchronous Transfer Mode) switches using neural networks. To avoid blocking in ATM switches with blocking characteristics, it is required to buffer ATM cells in input buffer and to schedule them. The N$\times$N request matrix is divided into N/16 submatrices in order to get rid of internal blocking systematically in scheduling phase. The submatrices are grouped into N/4 groups, and the cells in each group are switched alternatively. As the window size of input buffer is increases, the number of input cells switched in a time slot approaches to N. The selection of nonblocking cells to be switched is done by neural network modules. N/4 neural network modules are operated simultaneously. Fast selection can be achieved by massive parallelism of neural networks. The neural networks have 4N neurons and 14N connection. The proposed method is implemented in C language, and the simulation result confirms the feasibility of this method.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1103-1104
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• 2008

In this paper, authors propose a novel step-up AC-DC chopper operated with power factor correction (PFC) and with high efficiency. The proposed chopper behaves with discontinuous current control (DCC) of input current. The input current waveform in the proposed chopper is got to be a discontinuous sinusoid form in proportion to magnitude of ac input voltage under the constant duty cycle switching. Therefore, the input power factor is nearly unity and the control method is simple. In the general DCC chopper, the switching devices are turned-on with the zero current switching, but turn-off of the switching devices is switched at current maximum value. To achieve a soft switching of the switching turn-off, the proposed chopper is used a new partial resonant circuit. The result is that the switching loss is very low and the efficiency of chopper is high.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.160-163
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• 2000

In this paper, we propose an efficient technique to minimize the input offset of a dynamic latch comparator. We analyzed offset due to charge injection mismatching and unwanted positive feedback during sampling phase. The last one was only considered in the previous works. Based on the analysis, we proposed a modified dynamic latch with initialization switch. The proposed circuit was simulated using 0.65$\mu\textrm{m}$ CMOS process parameter with 5v supply. The simulation results showed that the input offset is less than 5mv at 200㎒ sampling frequency and the input offset is improved about 80% compared with previous work in 5k$\Omega$ input resistance.