• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1996.06a
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• pp.153-158
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• 1996

Delay and jitter are critical factors in the real-time video services over ATM network. Mostly, delay and jitter problem are generated in input buffer when video are multiplexed. In this paper, we analyze delay and jitter of input buffer, and consider efficient control and flexible bandwidth allocation of video traffic. Also, we analyze decision of buffer size related maximum allowable delay.

• Korean Journal of Computational Design and Engineering
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• v.15 no.2
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• pp.115-123
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• 2010

We present an efficient algorithm for computing the Hausdorff distance between two planar curves. The algorithm is based on an efficient trimming technique that eliminates the curve domains that make no contribution to the final Hausdorff distance. The input curves are first approximated with biarcs within a given error bound in a pre-processing step. Using the biarc approximation, the distance map of an input curve is then approximated and stored into the graphics hardware depth-buffer by rendering the distance maps (represented as circular cones) of the biarcs. We repeat the same procedure for the other input curve. By sampling points on each input curve and reading the distance from the other curve (stored in the hardware depth-buffer), we can easily estimate a lower bound of the Hausdorff distance. Based on the lower bound, the algorithm eliminates redundant curve segments where the exact Hausdorff distance can never be obtained. Finally, we employ a multivariate equation solver to compute the Hausdorff distance efficiently using the remaining curve segments only.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.5
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• pp.123-133
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• 1994

This paper presents an output arbitrator for input buffering ATM (Asynchronous Transfer Mode) switches using neural networks. To avoid blocking in ATM switches with blocking characteristics, it is required to buffer ATM cells in input buffer and to schedule them. The N$\times$N request matrix is divided into N/16 submatrices in order to get rid of internal blocking systematically in scheduling phase. The submatrices are grouped into N/4 groups, and the cells in each group are switched alternatively. As the window size of input buffer is increases, the number of input cells switched in a time slot approaches to N. The selection of nonblocking cells to be switched is done by neural network modules. N/4 neural network modules are operated simultaneously. Fast selection can be achieved by massive parallelism of neural networks. The neural networks have 4N neurons and 14N connection. The proposed method is implemented in C language, and the simulation result confirms the feasibility of this method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2003.10a
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• pp.373-376
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• 2003

This paper presents a new, three-dimensional round-robin scheduler that provides high throughput and fair across in an advanced input-queued packet switch using shared input buffers. We consider an architecture in which each input port group shares a common buffer and maintains a separate queue for each output, which is ratted the distributed common input buffer switch. In an NxN switch, our scheduler determines which queue in the total MxN input queues is served during each time slot where M is the number of common buffers. We suppose that each common buffer has K input ports and K output ports, and manages N output queues. The 3DRR scheduler determines MxK queues in every K(M) cycle when $K\geq$M (K$\leq$M), and provides massively parallel processing for the applications of high-speed switches with a large number of ports. The 3-DRR scheduler can be implemented using duplicated simple logic components allowing very high-speed implementation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.12 no.4
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• pp.71-79
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• 2016

This study proposes a performance model of a shared bus multi-processor system and analyzes the effect of input/output types on system performance and overload of shared resources. This system performance model reflects the memory reference time in relation to the effect of input/output types on shared resources and the input/output processing time in relation to the input/output processor, disk buffer, and device standby places. In addition, it demonstrates the contribution of input/output types to system performance for comprehensive analysis of system performance. As the concept of workload in the probability theory and the presented model are utilized, the result of operating and analyzing the model in various conditions of processor capability, cache miss ratio, page fault ratio, disk buffer hit ratio (input/output processor and controller), memory access time, and input/output block size. A simulation is conducted to verify the analysis result.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.1
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• pp.79-83
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• 2004

The purpose of ATM traffic management is to protect the network using minimum resources and guarantee the requred QoS and also it is desirable to provide fairness between input channels. In this paper, we propose the TBBM(threshold based buffer management) algorithm to improve fairness between input channels and utilization of ATM networks. TBBM algorithm controls output cell rate dynamically based on threshold. The result shows that the required bandwidth of the TBBM algorithm is 14.3% lower in audio traffic and 41.8% lower in video traffic than that of theoretically calculated equivalent capacity method. and also reveals that the TBBM algorithm provide improved CLR fairness between input channels

• International Journal of Control, Automation, and Systems
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• v.6 no.2
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• pp.214-222
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• 2008

Bode principle is applied to carry out traffic control for rate based ATM network, which guarantees the higher buffer utilization, buffer overflow-free, and well utilization of bandwidth. The principle confirms the relationship between the threshold of buffer queue and the network bandwidth, as well as the relationship between the threshold of buffer and source input rate. Theoretic warrant of the buffer threshold is proposed. The reference range of source input rate is provided in theory, which makes the source end respond to the change of network state rapidly and dynamically, and then the effect of time delay to the traffic control is avoided. Simulation results show that the better steady and dynamic performances of networks are obtained by Bode principle.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.561-564
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• 1998

This paper describes a performance degradation of static type input buffer due to the device degradation in menory devices using $0.8\mu\textrm{m}$ CMOS process. experimental results shows that the degradation of MOS device affects the Trip Point shift in static type input buffer. We have performed the spice simulation and calculated the Trip Point with model parameter and measurement data so that how much the Trip Point(VLT) variate.

• Journal of Korean Institute of Industrial Engineers
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• v.16 no.2
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• pp.81-89
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• 1990

Transfer pricing mechanism is applied to the problem of input buffer size in the context of interfacing a flexible manufacturing system with multiple following production lines. The size of the input buffers can be determined economically by using non-linear transfer pricing either in a decentralized organization or in a centralized organization. Under the certain conditions, input buffer size determined from this non-linear transfer pricing is more economical than the traditional economic lot size model. The benefit comes from transferring part of FMS' inventory to the following production lines. And this non-linear transfer pricing makes sense if the FMS' unit inventory holding cost is high enough.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1170-1173
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• 1987

A network flow control method, input buffer limit technique which can adjusts the transit traffics in a node, is proposed. The transit traffics that occupy node buffers more threshold are decreased. It has better performance than input buffer limit. The proposed flow control is analyzed by queueing model. Numerical results of some example are shown.