• 한국정보과학회:학술대회논문집
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• 한국정보과학회 2008년도 한국컴퓨터종합학술대회논문집 Vol.35 No.1 (A)
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• pp.329-330
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• 2008

• Journal of information and communication convergence engineering
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• 제7권1호
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• pp.62-65
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• 2009

In this paper, the temperature characteristics of full CMOS FLL(frequency locked loop) re analyzed. The FLL circuit is used to generate an output signal that tracks an input efference signal. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. Also the FLL s designed to allow the circuit to be fully integrated. The FLL circuit is composed two VCs, two buffers, a VCO and two frequency dividers. The temperature variation of frequency divider, FVC and buffer cancelled because the circuit structure. is the same and he temperature effect is cancelled by the comparator. Simulation results are shown to illustrate the performance of the designed FLL circuit with temperature.

• 대한수학회보
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• 제43권3호
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• pp.657-669
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• 2006

In this paper, we analyze a leaky bucket (LB) scheme with queue length dependent arrival rates. In other words, if the queue length exceeds an appropriate threshold value on buffer, the arrivals need to be controlled. In ATM networks, if the congestion occurs, the input traffics must be controlled (reduced) for congestion resolution. By the bursty and correlated properties of traffics, the arrivals are assumed to follow a Markov-modulated Poisson process (MMPP). We derive the loss probability and the waiting time distribution for arbitrary cell. The analysis is done by using the embedded Markov chain and supplementary variable method. We also present some numerical examples to show the effects of our proposed LB scheme.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(II)
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• pp.1488-1491
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• 1987

This paper describes 16-point FFT processor using systolic array and its implementation into VLSI. Designed FFT processor executes FFT/IFFT arithmetic under mode control and consists of cell array, array controller and input/output buffer memory. For design for testibility, we added built-in self test circuit into designed FFT processor. To verify designed 16-point FFT processor, logic simulation was performed by YSLOG on MICRO-VAXII. From the simulation results, it is estimated that the proposed FFT processor can perform 16-point FFT in about 4400[ns].

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 하계종합학술대회논문집
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• pp.126-129
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• 1998

In order to control the flow of traffics in ATM networks and optimize the usage of network resources, an efficient control mechanism is necessary to cope with congestion and prevent the degradation of network performance caused by congestion. This paper proposes a new UPC(Usage Parameter Control) mechanism that varies the token generation rate and the buffer threshold of leaky bucket by using a Neural Network controller observing input buffers and token pools, thus achieving the improvement of performance. Simulation results show that the proposed adaptive algorithm uses of network resources efficiently and satisfies QoS for the various kinds of traffics.

• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2004년도 춘계학술대회 학술발표 논문집 제14권 제1호
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• pp.17-21
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• 2004

본 논문에서는 실시간으로 상수 및 변수의 병렬 매칭이 가능한 새로운 구조의 하드웨어 기반 룰-베이스시스템 구조를 제안한다. 이 시스템은 context-aware computing 시스템에서 상황 인식을 위한 기법으로 적용될 수 있다. 제안된 구조는 기존의 하드웨어 기반의 구조가 가지는 룰의 표현 및 룰의 구성에서 발생하는 제약을 상당히 감소시킬 수 있다. 이를 위해 변형된 형태의 content addressable memory(CAM)와 crossbar switch network(CSN)가 사용되었다. 변형된 형태의 CAM으로 구성된 지식-베이스는 동적으로 데이터의 추가 및 삭제가 가능하다. 또한 CSN은 input buffer와 working memory(WM) 사이에 위치하여, 시스템 외부 및 내부에서 동적으로 생성되거나, 시스템 설정에 의해 지정된 데이터들의 조합 및 pre-processing module(PPM)을 이용한 연산을 통하여 WM을 구성하는 데이터를 생성시킨다. 이 하드웨어 룰-베이스 시스템은 SystemC 2.0을 이용하여 설계하였으며 시뮬레이션을 통하여 그 동작을 검증하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.72-75
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• 2003

For the analog output buffer in the data driver for large size and high resolution TFT-LCDs, we proposed operational amplifier (op-amp) which contains newly developed transconductance-boosted input stage which enables the low-power consumption and the high slew-rate. The slew-rate and the quiescent current of the proposed op-amp are $6.1V/{\mu}sec$ and $8{\mu}A$, respectively.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.68.1-68
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• 2001

This paper discusses tracking position control of linear actuator that has a time delay. The time delay happens when the process reads the sensor data and sends the control input to the plant located at a remote site in distributed control system. In this thesis, the time delay between the linear actuator and the discrete PID controller has constant value due to buffer device so the time delay can be modeled by Pade approximation but the large position error of the linear actuator is generated by the time delay. Therefore, the Smith predictor is used for tracking position control of the linear actuator with the time delay in order to minimize the effect of the time delay. The experimental and simulation results show that the ...

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.927-930
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• 2003

In this paper, a design of processor IP for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability. To handle the various modes of TCP/IP protocol, hardware and software co-design approach is used rather than the conventional state machine based design. To eliminate delay time due to the data transfer and checksum operation, DAM module which can execute the checksum operation on-the-fly along with data transfer operation is adopted. By programming the on-chip code ROM of RISC processor differently. the designed stack processor can support the packet format conversion operations required in the various TCP/IP protocols.

• 대한전자공학회논문지
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• 제16권1호
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• pp.14-21
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• 1979

본 논문에서는 FSK 통신을 사용한 전자계산기의 On-Line 계통에서의 오차를 연구하였으며 수신측의 발광주파수 피상을 송신측에 일치시키는 회로를 설계함으로써 4 % 이내의 주파수 편이에서도 동작이 가능하게 하였다. 또한 On-Line 계통에서 비트 오차를 계산하기 위하여는 Micro-processor를 사용하였고, 발생된 대부분의 오차는 FSK 통신계통에 의한 것이었으며, 본 연구에서 설계한 방식을 사용함으로써 완위레지스터에서 마이브로프로서로 입력되는 오차는 매우 적게 되었다.