• The Transactions of the Korea Information Processing Society
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• v.7 no.11S
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• pp.3684-3693
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• 2000

In this paper, performance of a nonblocking high speed packet switch with switching capacity m which adopts a dynamic priority control function (DPCF) of a threshold- based Bernoulli priority jump (TBPJ) scheme is considered. Each input queue has two separate buffers with different sizes for two classes of traffics, delay-sensitive and loss-sensitive traffics, and adopts a TBPJ scheme that is a general state-dependent Bernoulli scheduling scheme. Under the TBP] scheme, a head packet of the delay-sensitive traffic buffer goes into the loss -sensitive traffic buffer with Hernoulli probability p according to systems states that represent the buffer thresholds and the number of packets waiting for scheduling. Performance analysis shows that TBPJ scheme obtains large performance build-up for the delay-sensitive traffic without performance degradation for the loss-sensitive traffic. In addition to, TBP] scheme shows better performance than that of HOL scheme.

• The Journal of the Korea institute of electronic communication sciences
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• v.16 no.1
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• pp.69-74
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• 2021

This paper introduces a low-power voltage-controlled oscillator(VCO) with filters that consist of resistors and capacitors. The proposed VCO contains a 5-stage current mode buffer, and each buffer cell has a resistor-capacitor filter that connects input and output terminals. The filter adds a zero to the buffer cell. Because the zero moves the oscillation condition to high frequencies, the proposed VCO can generate a high frequency clock with low power consumption. The proposed circuit has been designed with 0.18 ㎛ CMOS process. The power consumption is 9.83 mW at 2.7 GHz. The proposed VCO shows 3.64 pJ/Hz in our simulation study, whereas the conventional circuit shows 4.79 pJ/Hz, indicating that our VCO achieves 24% reduction in power consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.13-22
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• 2010

This paper proposed the dual-loops multiphase DLL based mixed VCO/VCDL for a high frequency phase noise suppression of the input clock and the multiple frequencies generation with a precise duty cycle. In the proposed architecture, the dual-loops DLL uses the dual input differential buffer based nMOS source-coupled pairs at the input stage of the mixed VCO/VCDL. This can easily convert the input and output phase transfer of the conventional DLL with bypass pass filter characteristic to the input and output phase transfer of PLL with low pass filter characteristic for the high frequency input phase noise suppression. Also, the proposed DLL can correct the duty-cycle error of multiple frequencies by using only the duty-cycle correction circuits and the phase tracking loop without additional correction controlled loop. At the simulation result with $0.18{\mu}m$ CMOS technology, the output phase noise of the proposed DLL is improved under -13dB for 1GHz input clock with 800MHz input phase noise. Also, at 1GHz operating frequency with 40%~60% duty-cycle error, the duty-cycle error of the multiple frequencies is corrected under $50{\pm}1%$ at 2GHz the input clock.

• The Transactions of the Korea Information Processing Society
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• v.3 no.4
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• pp.947-960
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• 1996

The primary goal for developing high performance ATM switching systems is to minimized the probability of cell loss, cell delay and deterioration of throughput. ATM switching element that is the most suitable for this purpose is the shared buffer memory switch executed by common random access memory and control logic. Since it is difficult to manufacture VLIS(Very Large Scale Integrated circuit) as the number of input ports increased, the used of switching module method the realizes 32$\times$32, 150 Mb/s switch utilizing 8$\times$8, 600Mb/s os 16$\times$16, 150Mb/s unit switch is latest ATM switching technology for small and large scale. In this paper, buffer capacity satisfying total-memory-reduction effect by buffer sharing in a shared buffer memory switch are analytically evalu ated and simulated by computer with cell loss level at traffic conditions, and also features of switching network utilizing the switching module methods in small and large-capacity ATM switching system is analized. Based on this results, the structure in outline of 32$\times$32(4.9Gb/s throughput), 150Mb/s switches under research in many countries is proposed, and eventually, switching-network structure for ATM switching system of small and large and capacity satisfying with above primary goals is suggested.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.3
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• pp.179-196
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• 1986

In this paper, the peformance of a statistical packet voice/data multiplexer is studied. In ths study we assume that in the packet voice/data multiplexer two separate finite queues are used for voice and data traffics, and that voice traffic gets priority over data. For the performance analysis we divide the output link of the multiplexer into a sequence of time slots. The voice signal is modeled as an (M+1) - state Markov process, M being the packet generation period in slots. As for the data traffic, it is modeled by a simple Poisson process. In our discrete time domain analysis, the queueing behavior of voice traffic is little affected by the data traffic since voice signal has priority over data. Therefore, we first analyze the queueing behavior of voice traffic, and then using the result, we study the queueing behavior of data traffic. For the packet voice multiplexer, both inpur state and voice buffer occupancy are formulated by a two-dimensional Markov chain. For the integrated voice/data multiplexer we use a three-dimensional Markov chain that represents the input voice state and the buffer occupancies of voice and data. With these models, the numerical results for the performance have been obtained by the Gauss-Seidel iteration method. The analytical results have been verified by computer simylation. From the results we have found that there exist tradeoffs among the number of voice users, output link capacity, voic queue size and overflow probability for the voice traffic, and also exist tradeoffs among traffic load, data queue size and oveflow probability for the data traffic. Also, there exists a tradeoff between the performance of voice and data traffics for given inpur traffics and link capacity. In addition, it has been found that the average queueing delay of data traffic is longer than the maximum buffer size, when the gain of time assignment speech interpolation(TASI) is more than two and the number of voice users is small.

• Journal of IKEEE
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• v.5 no.1 s.8
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• pp.100-110
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• 2001

In this paper, we investigated several buffer management schemes for the design of shared-memory type ATM switches, which can enhance the utilization of switch resources and can support quality-of-service (QoS) functionalities. Our results show that dynamic threshold (DT) scheme demonstrate a moderate degree of robustness close to pushout(PO) scheme, which is known to be impractical in the perspective of hardware implementation, under various traffic conditions such as traffic loads, burstyness of incoming traffic, and load non-uniformity across output ports. Next, we considered buffer management strategies to support QoS functions, which utilize parameter values obtained via connection admission control (CAC) procedures to set tile threshold values. Through simulations, we showed that the buffer management schemes adopted behave well in the sense that they can protect regulated traffic from unregulated cell traffic in allocating buffer space. In particular, it was observed that dynamic partitioning is superior in terms of QoS support than virtual partitioning.

• Tunnel and Underground Space
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• v.31 no.4
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• pp.221-242
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• 2021

A numerical study of the performance assesment of coupled thermo-hydro-mechanical (THM) processes in improved Korean reference disposal system (KRS⁺) for high-level radioactive waste is conducted using TOUGH2-MP/FLAC3D simulator. Decay heat from high-level radioactive waste increases the temperature of the repository, and it decreases as decay heat is reduced. The maximum temperature of the repository is below a maximum temperature criterion of 100℃. Saturation of bentonite buffer adjacent to the canister is initially reduced due to pore water evaporation induced by temperature increase. Bentonite buffer is saturated 250 years after the disposal of high-level radioactive waste by inflow of groundwater from the surrounding rock mass. Initial saturation of rock mass decreases as groundwater in rock mass is moved to bentnonite buffer by suction, but rock mass is saturated after inflow of groundwater from the far-field area. Stress changes at rock mass are compared to the Mohr-Coulomb failure criterion and the spalling strength in order to investigate the potential rock failure by thermal stress and swelling pressure. Additional simulations are conducted with the reduced spacing of deposition holes. The maximum temperature of bentonite buffer exceeds 100℃ as deposition hole spacing is smaller than 5.5 m. However, temperature of about 56.1% volume of bentonite buffer is below 90℃. The methodology of numerical modeling used in this study can be applied to the performance assessment of coupled THM processes for high-level radioactive waste repositories with various input parameters and geological conditions such as site-specific stress models and geothermal gradients.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.8
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• pp.22-26
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• 2012

This paper introduces a 2.5-Gb/s optical receiver implemented in a standard 1P4M 0.18um CMOS technology for the applications of active optical HDMI cables. The optical receiver consists of a differential transimpedance amplifier(TIA), a five-stage differential limiting amplifier(LA), and an output buffer. The TIA exploits the inverter input configuration with a resistive feedback for low noise and power consumption. It is cascaded by an additional differential amplifier and a DC-balanced buffer to facilitate the following LA design. The LA consists of five gain cells, an output buffer, and an offset cancellation circuit. The proposed optical receiver demonstrates $91dB{\Omega}$ transimpedance gain, 1.55 GHz bandwidth even with the large photodiode capacitance of 320 fF, 16 pA/sqrt(Hz) average noise current spectral density within the bandwidth (corresponding to the optical sensitivity of -21.6 dBm for $10^{-12}$ BER), and 40 mW power dissipation from a single 1.8-V supply. Test chips occupy the area of $1.35{\times}2.46mm^2$ including pads. The optically measured eye-diagrams confirms wide and clear eye-openings for 2.5-Gb/s operations.

• Journal of Korea Society of Industrial Information Systems
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• v.19 no.4
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• pp.17-24
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• 2014

In this paper, we propose a CMOS FM RX front-end structure with an automatic tunable input matching network and implement it using a 65nm CMOS technology. The proposed FM RX front-end is designed to change the resonance frequency of the input matching network at the low noise amplifier (LNA) according to the channel frequency selected by a phase-locked loop (PLL) for maintaining almost constant sensitivity level when an embedded antenna type with high frequency selectivity characteristic is used for FM receiver. The simulation results of implemented FM front-end show about 38dB of voltage gain, below 2.5dB of noise figure, and -15.5dBm of input referred intercept point (IIP3) respectively, while drawing only 3.5mA from 1.8V supply voltage including an LO buffer.

• Journal of Internet Computing and Services
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• v.3 no.3
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• pp.87-93
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• 2002

A complex network and a parallel computer are made up of interconnected switching units. The role of a switching unit is to set up a connection between an input port and an output port, according to the routing information. We proposed our switching network with a remodeled architecture is a newly modified Banyan network with eight input and output ports. We have analysed the maximum throughput of the revised switch. Our analyses have shown that under the uniform random traffic load, the FIFO discipline is limited to 70%, The switching system consists of an input control unit, a switch unit and an output control unit. Therefore the result of the analyses shows that the results of the networking simulation with the new switch are feasible and if we adopt the new architecture of the revised model of the Banyan switch, the hardware complexity can be reduced. The FIFO discipline has increased by about 11% when we compare the switching system with the input buffer system. We have designed and verified the switching system in VHDL using Max＋plusII. We also designed our test environment including micro computers, the base station, and the proposed architecture. We proposed a new architecture of the Banyan switch for BISDN networks and parallel computers.