• Korean Journal of Materials Research
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• v.21 no.10
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• pp.532-541
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• 2011

The Xe plasma flat lamp, considered to be a new eco-friendly LCD backlight, requires a further improvement of its luminance and luminous efficiency. To improve the performance of this type of lamp, it is necessary to understand the effects of the discharge variables on the luminous characteristics of the lamp. In this study, the luminous characteristics of a coplanartype Xe plasma flat lamp with a teeth-type electrode pattern were analyzed while varying the gas composition, gas pressure and input voltage. The effects of the phosphor layer on the discharge and the luminous characteristics of the lamp were also studied. The luminous efficiency of the coplanar-type Xe plasma flat lamp improved as the Xe input ratio and gas pressure increased. Higher luminous efficiency was also obtained when helium (He) was used as a buffer gas and when a phosphor layer was fabricated on the electrode region. In contrast, the luminous efficiency was reduced with increasing the input voltage. It was found that the infrared emissions from the lamp were affected by the Xe excitation rate in the plasma, the Xe gas density, the collisional quenching of excited Xe species by gas molecules, and the recombination rate between the Xe ions and electrons.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.3
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• pp.14-21
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• 1989

In the digital transmission equipment, the input jitter tolerance is a function of input timing recovery circuit characteristics. Especially, in the asynchronous multiplexers, it is also a function of the frame format, the buffer sizes in the synchronizer and desynchronizer, the PLL transfer function, and operating range of VCO in PLL In this paper, a new algorithm for calculating the jitter tolerance of the saynchronous digital transmission equipment is presented. With the new algorithm, we analyzed how the above factors limit the jitter tolerance in the equipment. We also measured the input jitter tolerance for a 45M-140M multiplexing equipment, whose results show the same trend with calculated tolerance.

• Spatial Information Research
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• v.15 no.4
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• pp.363-370
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• 2007

This study has been carried for the development of the basic algorithm of helicopter navigation system based on TRN (Terrain Referenced Navigation) with information input from the GPS. The helicopter determines flight path due to Origination-Destination analysis on the Cartesian coordinate system of 3-D DTM. This system shows 3-D mesh map and the O-D flight path profile for the pilot's acknowledgement of the terrain, at first. The system builds TCF (terrain clearance floor) far the buffer zone upon the surface of ground relief to avid the ground collision. If the helicopter enters to the buffer zone during navigation, the real-time warning message which commands to raise the body pops up using Matlab menu. While departing or landing, control of the height of the body is possible. At present, the information (x, y, z coordinates) from the GPS is assumed to be input into the system every 92.8 m of horizontal distance while navigating along flight path. DTM of 3" interval has been adopted from that which was provided by ChumSungDae Co., Ltd..

• Journal of the Korean Institute of Telematics and Electronics B
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• v.30B no.9
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• pp.94-105
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• 1993

In this paper propose a Koaren character recognition system using a neural network is proposed. This system is a multilayer neural network based on the masking field model which consists of a input layer, four feature extraction layers which extracts type, direction, stroke, and connection features, and an output layer which gives us recognized character codes. First, 4x4 subpatterns of an NxN character pattern stored in the input buffer are applied into the feature extraction layers sequentially. Then, each of feature extraction layers extracts sequentially features such as type, direction, stroke, and connection, respectively. Type features for direction and connection are extracted by the type feature extraction layer, direction features for stroke by the direction feature extraction layer and stroke and connection features for stroke by the direction feature extraction layer and stroke and connection features for the recongnition of character by the stroke and the connection feature extractions layers, respectively. The stroke and connection features are saved in the sequential buffer layer sequentially and using these features the characters are recognized in the output layer. The recognition results of this system by tests with 8 single consonants and 6 single vowels are promising.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.7-13
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• 2002

When a USB digital camera is used for PC video-conference applications, motion picture data need to be transferred to the PC through the USB port. Due to the mismatch between the data rates of the USB and the motion picture, data compression should be performed before the transmission from the USB. While many motion picture compression algorithms require large intermediate memory space, the JPEG algorithm does not need to store an entire frame for the compression. Instead, a relatively small buffer is required at the input of the JPEG compression engine to resolve the inconsistency between the orders of the inputted data and the consumed data. Data reordering can be easily implemented using a double buffering scheme, which still requires a considerable size of memory. In this paper, a novel memory management scheme is proposed to avoid the double buffering. The proposed memory architecture requires a small amount of memory and a simple address generation scheme, resulting in overall cost reduction.

• Journal of Advanced Navigation Technology
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• v.19 no.1
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• pp.66-73
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• 2015

In this paper, an architecture of a perpetual smart video device and its energy control model for the internet of things (IoT) are proposed. The smart video device consists of a processor, an image sensor, a video codec, and a network controller. In the proposed energy control model, energy consumed by image sensing, video encoding, and transmission and energy harvested by solar panels are defined as an input and an output of a battery, an energy buffer. Frame rate, quantization parameter, and operating frequency of processor are defined as the energy control parameters, and these parameters control the input and the output energy of the energy buffer, finally control the energy left in the battery. The proposed energy control model is validated by the energy consumption measurement of the smart phone based platform for various combinations of energy control parameters, and can be used for the design of perpetual smart video device.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.6
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• pp.1166-1174
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• 2004

In this paper, a design of RISC-based transmission wrapper processor for TCP/IP protocol stack is described. The processor consists of input and output buffer memory with dual bank structure, 32-bit RISC microprocessor core, DMA unit with on-the-fly checksum capability, and memory module. To handle the various modes of TCP/IP protocol, hardware-software codesign approach based on RISC processor is used rather than the conventional state machine design. To eliminate large delay time due to sequential executions of data transfer and checksum operation, DMA module which can execute the checksum operation along with data transfer operation is adopted. The designed processor exclusive of variable-size input/output buffer consists of about 23,700 gates and its maximum operating frequency is about 167MHz under 0.35${\mu}m$ CMOS technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.10a
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• pp.398-401
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• 2011

This paper presents a high-efficiency CMOS PWM DC-DC buck converter. It generates a constant output voltage(1-2.8V), from an input voltage(3.4-3.9V). Inductor-based type is chosen and inductor current is controlled with PWM operation. The designed circuit consists of power switch, Pulse Width Generation, Buffer, Zero Current Sensing, Current Sensing Circuit, Clock & Ramp generation, V-I Converter, Soft Start, Compensator and Modulator. Switching Frequency is 1MHz, It operates in CCM when the load current is more than 40mA, and the maximum efficiency is 98.71% at 100mA. Output voltage ripple is 0.98mV(input voltage:3.5V, output voltage:2.5V). The performance of the designed circuit has been verified through extensive simulation using a CMOS $0.18{\mu}m$ technology.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1184-1195
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• 1998

In this paper, we compare vaious input-buffered ATM switch architectures in structures on input buffer and switching fabric, the resons for performance improvement and degradation, arbitration scheme and maximum throughput, and present comparative merits and demerits of each architecture under random and bursty traffic. We also analyze the prformance of combined architectures of windowing scheme, destination-queueing based input-port expansion schemeand output-port expansion scheme, and show that it is possible to achieve 100% throughput with combined scheme of destination-queueing based input-port expansion scheme and output-port expansio scheme when the number of output group is 2 and output port expansion ratio is 2.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.3
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• pp.433-437
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• 2015

We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using $0.35{\mu}m$ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 V.