• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.180-182
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• 2001

Input Current Correction of Single-Phase Buck Rectifier is studied in the paper. To sinusoidal waveform the input current with a near-unity power factor over a wide variety of operating conditions, the output capacitor is operated with voltage reversibility for the supply by arranging the auxiliary diode and power switching device. Then the output voltage is superposed on the input voltage during on time duration of power switching devices in order to minimize the input current distortion caused by the small input voltage when changing the polarity. The tested setup, using two insulated-gate bipolar transistors(IGBT) and a microcomputer, is implemented and IGBT are switched with 20[kHz], which is out of the audible band. Moreover, a rigorous state-space analysis is introduced to predict the operation of the rectifier. The simulated results confirm that the input current can be sinusoidal waveform with a near-unity power factor and a satisfactory output voltage regulation can be achieved.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.2
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• pp.209-215
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• 2018

This paper present a 7-level PWM inverter adopting voltage balancing control to series-connected input capacitors. The prior proposed 7-level PWM inverter consists of dc input source, three series-connected capacitors, two bidirectional switch modules, and an H-bridge. This circuit topology is useful to increase the number of output voltage levels, however it fails to generate 7-level in output voltage without consideration for voltage balancing among series-connected capacitors. Capacitor voltage imbalance is caused on the different period between charging and discharging of capacitor. To solve this problem, we uses the amplitude modulation of carrier wave, which is used to produce the center output voltage level. To verify the validity of the proposed control method, we carried out computer-aided simulation and experiments using a prototype.

• Proceedings of the KIEE Conference
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• 2015.07a
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• pp.1018-1019
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• 2015

Recently, standby power reduction techniques of AC/DC adaptor were developed, consuming power almost arrived to 300mW level. The standby power losses are composed of the input filter loss 11.8mW, the control IC for AC/DC adaptor 18mW, the switching loss 9.53mW and the feedback loss 123mW. And there are the standby power reduction techniques. In this paper, in order to reduce the standby power of SMPS more, the loss due to a voltage difference between input and output is reduced by the control circuit which is composed of the low voltage driving circuit and voltage regulator. The low voltage driving circuit operates on the low voltage of input and off the high voltage. The low voltage driving IC was produced by the $1.0{\mu}m$, high voltage DMOS process.

• 한국정보디스플레이학회:학술대회논문집
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• 2002.08a
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• pp.560-562
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• 2002

The liquid crystal(LC) pixel capacitance Clc, which varies as a function of applied pixel voltage, is a main factor of pixel voltage errors on input gamma voltage, and therefore of the electro-optics(E-O) characteristics of LC pixel for a-Si TFT LCDs. The pixel voltage error(${\Delta}$Vp) for input gamma voltage was simulated for 14.1 inch diagonal XGA panel. An agreement between the experimental results and simulation was satisfactory for the gamma voltage compensation, ${\Delta}$Vp of the input gamma voltage. The proposed compensation method was successfully introduced to a 14.1 inch diagonal XGA panel, and a remarkable improvement of image sticking was achived.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.61 no.10
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• pp.1432-1441
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• 2012

In this study, an improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source inverter(Improved LCCT ZSI) with characteristics of Quasi Z-source inverter(QZSI) and LCCT Z-source inverter(LCCT ZSI) is proposed. The proposed inverter can also reduce the voltage stress and input current/capacitor voltage ripples compared with conventional LCCT ZSI and Quasi ZSI. A two winding trans in Z-impedance network of the conventional LCCT ZSI is replaced by a three winding trans in the proposed inverter. To verify the validity of the proposed inverter, a DSP controlled hardware was made and PSIM simulation was executed for each method. Comparing the current and voltage ripples of each method under the condition of input DC voltage 70[V] and output AC voltage 76[Vrms], the input current and capacitor voltage ripple factors of the proposed inverter were low as 11[%] and 1.4[%] respectively. And, for generation of the same output AC voltage of each method, voltage stress of the proposed inverter was low as 175[V] under the condition of duty ratio D=0.15. As mentioned above, we could know that the proposed inverter have the characteristics of low voltage stress, low ripple factor and low operation duty ratio compared with the conventional methods. Finally, the efficiency according to load change/duty ratio and the transient state characteristics were discussed.

• Proceedings of the KIPE Conference
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• 1996.06a
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• pp.85-88
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• 1996

New power factor correction(PFC) technique based on the averaged model of boost converter is proposed. Without measurement of input current, power factor correction scheme derived from the averaged model is presented. With the measurements of input voltage and output voltage, the control signal is generated to make the shape of the line current same as the input voltage. The characteristics of input line current distortion is analyzed by considering the generation of duty cycle.

• Journal of Electrical Engineering and Technology
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• v.9 no.5
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• pp.1632-1642
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• 2014

This paper presents an interleaved resonant converter to reduce the voltage stress of power MOSFETs and achieve high circuit efficiency. Two half-bridge converters are connected in series at high voltage side to limit MOSFETs at $V_{in}/2$ voltage stress. Flying capacitor is used between two series half-bridge converters to balance two input capacitor voltages in each switching cycle. Variable switching frequency scheme is used to control the output voltage. The resonant circuit is operated at the inductive load. Thus, the input current of the resonant circuit is lagging to the fundamental input voltage. Power MOSFETs can be turn on under zero voltage switching. Two resonant circuits are connected in parallel to reduce the current stress of transformer windings and rectifier diodes at low voltage side. Interleaved pulse-width modulation is adopted to decrease the output ripple current. Finally, experiments are presented to demonstrate the performance of the proposed converter.

• Proceedings of the KIPE Conference
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• 2019.07a
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• pp.83-85
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• 2019

The use of high voltage gain converters is essential for the distributed power generation systems with renewable energy sources such as the fuel cells and solar cells due to their low voltage characteristics. In this paper, a high voltage gain topology combining cascode Inverting Buck-Boost converter and voltage multiplier structure is introduced. In proposed converter, the input voltage is connected in series at the output, the portion of input power is directly delivered to the load which results in continuous input current. In addition, the voltage multiplier stage stacked in proper manner is not only enhance high step-up voltage gain ratio but also significantly reduce the voltage stress across all semiconductor devices and capacitors. As a result, the high current-low voltage switches can be employed for higher efficiency and lower cost. In order to show the feasibility of the proposed topology, the operation principle is presented and the steady-state characteristic is analyzed in detail. A 380W-40/380V prototype converter was built to validate the effectiveness of proposed converter.

• Journal of Power Electronics
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• v.15 no.3
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• pp.587-601
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• 2015

A high step-up dc-dc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switched-capacitor doubler and an active-clamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switched-capacitor doubler is composed of two symmetrical quasi-resonant switched-capacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switched-capacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverse-recovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the active-clamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulse-width modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.54 no.12
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• pp.616-621
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• 2005

We considered of the buck and half bridge series DC-DC converter. It has good applications in areas with low voltage/high current, wide input voltage. The buck converter ratings and the half bridge converter ratings are $36\~72V$ input and 22V/5A output, $19\~24V$ input and 3.3V/30A output, respectively. Developed the buck and half Bridge series DC-DC converter ratings are of $36\~72V$ input and 3.3V/30A output. The buck converter is operated with zero voltage switching process to reduce the switching losses. The $80.1\%\~97.6\%$ of the efficiency is measured at $18.4{\mu}H$ output filter inductance of buck converter. In the half bridge converter, the $86\%\~96.4\%$ efficiency is measured at 150kHz switching frequency with PQI core. In the case of synchronized the buck and half bridge DC-DC converter, the measured efficiency is higher than that of the unsynchronized converter. In the synchronized converter, the maximum efficiency is measured up to $92.3\%$ with PQI core at 150kHz. 7A output.