• Title/Summary/Keyword: Input Signal Generation

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Simulator for High Resolution Synthetic Aperture Radar Image Formation and Image Quality Analysis (고해상도 SAR 영상 형성 및 품질 분석을 위한 시뮬레이터)

  • Jung, Chul-Ho;Oh, Tae-Bong;Kwag, Young-Kil
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.18 no.8
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    • pp.997-1004
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    • 2007
  • High resolution synthetic aperture radar image could be sensitive to the various parameters of the payload, platform, and ground system. In this paper, a parameter based SAR simulator is presented for two-dimensional image formation and image quality analysis. Functional modules are implemented by Matalb code and GUI for the flexibility and expandability. Main function of this simulator includes the SAR input signal generation, range-doppler algorithm(RDA) based SAR image formation, and the SAR image quality analysis which is relevant to the SAR system design parameters. This simulator can effectively be used for the SAR image quality performance evaluation, which can be applicable to the airborne as well as spaceborne SAR system design and analysis.

Development of Verification and Conformance Testing Tools for Communication Protocol (통신 프로토콜 검정기 및 적합성시험 도구 개발)

  • Seo Mi-Seon;Hwang Jong-Gyu;Lee Jae-Ho;Kim Sung-Un
    • Journal of Korea Multimedia Society
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    • v.8 no.8
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    • pp.1119-1133
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    • 2005
  • As a very important part in development of the protocol, verification and conformance test for protocol specification are complementary techniques that are used to increase the level of confidence in the system functions as prescribed by their specifications. In this paper, we verify the safety and liveness properties of rail signal control protocol type 1 specified in LTS with model checking method, and experimentally prove that it is possible to check for the deadlock, livelock and rechability of the states and actions on LTS. The implemented formal checker is able to verify whether properties expressed in modal logic are true in specifications using modal mu-calculus. We also propose a formal method on generation of conformance test cases using the concept of UIO sequences from verified protocol specification. The suggested tools are implemented by C++ language under Windows NT.

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Generation of Changeable Face Template by Combining Independent Component Analysis Coefficients (독립성분 분석 계수의 합성에 의한 가변 얼굴 생체정보 생성 방법)

  • Jeong, Min-Yi;Lee, Chel-Han;Choi, Jeung-Yoon;Kim, Jai--Hie
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.6
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    • pp.16-23
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    • 2007
  • Changeable biometrics has been developed as a solution to problem of enhancing security and privacy. The idea is to transform a biometric signal or feature into a new one for the purposes of enrollment and matching. In this paper, we propose a changeable biometric system that can be applied to appearance based face recognition system. In the first step when using feature extraction, ICA(Independent Component Analysis) coefficient vectors extracted from an input face image are replaced randomly using their mean and variation. The transformed vectors by replacement are scrambled randomly and a new transformed face coefficient vector (transformed template) is generated by combination of the two transformed vectors. When this transformed template is compromised, it is replaced with new random numbers and a new scrambling rule. Because e transformed template is generated by e addition of two vectors, e original ICA coefficients could not be easily recovered from the transformed coefficients.

An exploratory study of stress wave communication in concrete structures

  • Ji, Qing;Ho, Michael;Zheng, Rong;Ding, Zhi;Song, Gangbing
    • Smart Structures and Systems
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    • v.15 no.1
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    • pp.135-150
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    • 2015
  • Large concrete structures are prone to cracks and damages over time from human usage, weathers, and other environmental attacks such as flood, earthquakes, and hurricanes. The health of the concrete structures should be monitored regularly to ensure safety. A reliable method of real time communications can facilitate more frequent structural health monitoring (SHM) updates from hard to reach positions, enabling crack detections of embedded concrete structures as they occur to avoid catastrophic failures. By implementing an unconventional mode of communication that utilizes guided stress waves traveling along the concrete structure itself, we may be able to free structural health monitoring from costly (re-)installation of communication wires. In stress-wave communications, piezoelectric transducers can act as actuators and sensors to send and receive modulated signals carrying concrete status information. The new generation of lead zirconate titanate (PZT) based smart aggregates cause multipath propagation in the homogeneous concrete channel, which presents both an opportunity and a challenge for multiple sensors communication. We propose a time reversal based pulse position modulation (TR-PPM) communication for stress wave communication within the concrete structure to combat multipath channel dispersion. Experimental results demonstrate successful transmission and recovery of TR-PPM using stress waves. Compared with PPM, we can achieve higher data rate and longer link distance via TR-PPM. Furthermore, TR-PPM remains effective under low signal-to-noise (SNR) ratio. This work also lays the foundation for implementing multiple-input multiple-output (MIMO) stress wave communication networks in concrete channels.

Activities and Planning for KRS Coordinates Maintenance

  • Kang, Hee Won;Cho, Sunglyong;Kim, Heesung;Yun, Youngsun;Lee, ByungSeok
    • Journal of Positioning, Navigation, and Timing
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    • v.11 no.4
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    • pp.327-332
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    • 2022
  • The Korea Augmentation Satellite System (KASS) is the Satellite-Based Augmentation System (SBAS) under development in Korea. KASS navigation service support navigation Safety of Life (SoL) service. KASS signal provides corrections to Global Positioning System (GPS) data received from KASS Reference Stations (KRS) and is broadcast form Geostationary Earth Orbiting (GEO) satellites to KASS users and is used by GPS/SBAS user equipment to improve the accuracy, availability, continuity and integrity of the navigation solution. Seven KRS's collect the satellite data and send them to the KASS Processing Stations (KPS) for the generation of the corrections and the monitoring the integrity. For performing its computation the KPS needs to know accurate and reliable KRS antennas coordinates. These coordinates are provided as configuration parameters to the KPS. This means that the reference frame in which the KPS work is the one represented by the set of coordinates provided as input. Therefore, the activity to maintain the accuracy of the KRS antenna coordinates is necessary, knowing that coordinates can evolve due to earth plates movements or earthquakes. In this paper, we analyzed the geodetic survey results for KRS antenna coordinates from Site Acceptance Test (SAT) #1 in December 2020 to August 2022. In the future, it is expected that these activities and planning for KRS coordinates maintenance will be produced and provided to KASS system operators for KPS configuration updates during the KASS lifetime of 15 years. Through these maintenance activities, it is expected that monitoring and analysis of unpredictable events such as earthquakes and seism will be possible in the future.

Efficient Data Representation of Stereo Images Using Edge-based Mesh Optimization (윤곽선 기반 메쉬 최적화를 이용한 효율적인 스테레오 영상 데이터 표현)

  • Park, Il-Kwon;Byun, Hye-Ran
    • Journal of Broadcast Engineering
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    • v.14 no.3
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    • pp.322-331
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    • 2009
  • This paper proposes an efficient data representation of stereo images using edge-based mesh optimization. Mash-based two dimensional warping for stereo images mainly depends on the performance of a node selection and a disparity estimation of selected nodes. Therefore, the proposed method first of all constructs the feature map which consists of both strong edges and boundary lines of objects for node selection and then generates a grid-based mesh structure using initial nodes. The displacement of each nodal position is iteratively estimated by minimizing the predicted errors between target image and predicted image after two dimensional warping for local area. Generally, iterative two dimensional warping for optimized nodal position required a high time complexity. To overcome this problem, we assume that input stereo images are only horizontal disparity and that optimal nodal position is located on the edge include object boundary lines. Therefore, proposed iterative warping method performs searching process to find optimal nodal position only on edge lines along the horizontal lines. In the experiments, we compare our proposed method with the other mesh-based methods with respect to the quality by using Peak Signal to Noise Ratio (PSNR) according to the number of nodes. Furthermore, computational complexity for an optimal mesh generation is also estimated. Therefore, we have the results that our proposed method provides an efficient stereo image representation not only fast optimal mesh generation but also decreasing of quality deterioration in spite of a small number of nodes through our experiments.

A Study on Efficient AI Model Drift Detection Methods for MLOps (MLOps를 위한 효율적인 AI 모델 드리프트 탐지방안 연구)

  • Ye-eun Lee;Tae-jin Lee
    • Journal of Internet Computing and Services
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    • v.24 no.5
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    • pp.17-27
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    • 2023
  • Today, as AI (Artificial Intelligence) technology develops and its practicality increases, it is widely used in various application fields in real life. At this time, the AI model is basically learned based on various statistical properties of the learning data and then distributed to the system, but unexpected changes in the data in a rapidly changing data situation cause a decrease in the model's performance. In particular, as it becomes important to find drift signals of deployed models in order to respond to new and unknown attacks that are constantly created in the security field, the need for lifecycle management of the entire model is gradually emerging. In general, it can be detected through performance changes in the model's accuracy and error rate (loss), but there are limitations in the usage environment in that an actual label for the model prediction result is required, and the detection of the point where the actual drift occurs is uncertain. there is. This is because the model's error rate is greatly influenced by various external environmental factors, model selection and parameter settings, and new input data, so it is necessary to precisely determine when actual drift in the data occurs based only on the corresponding value. There are limits to this. Therefore, this paper proposes a method to detect when actual drift occurs through an Anomaly analysis technique based on XAI (eXplainable Artificial Intelligence). As a result of testing a classification model that detects DGA (Domain Generation Algorithm), anomaly scores were extracted through the SHAP(Shapley Additive exPlanations) Value of the data after distribution, and as a result, it was confirmed that efficient drift point detection was possible.

Performance Analysis of a Statistical Packet Voice/Data Multiplexer (통계적 패킷 음성 / 데이터 다중화기의 성능 해석)

  • 신병철;은종관
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.11 no.3
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    • pp.179-196
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    • 1986
  • In this paper, the peformance of a statistical packet voice/data multiplexer is studied. In ths study we assume that in the packet voice/data multiplexer two separate finite queues are used for voice and data traffics, and that voice traffic gets priority over data. For the performance analysis we divide the output link of the multiplexer into a sequence of time slots. The voice signal is modeled as an (M+1) - state Markov process, M being the packet generation period in slots. As for the data traffic, it is modeled by a simple Poisson process. In our discrete time domain analysis, the queueing behavior of voice traffic is little affected by the data traffic since voice signal has priority over data. Therefore, we first analyze the queueing behavior of voice traffic, and then using the result, we study the queueing behavior of data traffic. For the packet voice multiplexer, both inpur state and voice buffer occupancy are formulated by a two-dimensional Markov chain. For the integrated voice/data multiplexer we use a three-dimensional Markov chain that represents the input voice state and the buffer occupancies of voice and data. With these models, the numerical results for the performance have been obtained by the Gauss-Seidel iteration method. The analytical results have been verified by computer simylation. From the results we have found that there exist tradeoffs among the number of voice users, output link capacity, voic queue size and overflow probability for the voice traffic, and also exist tradeoffs among traffic load, data queue size and oveflow probability for the data traffic. Also, there exists a tradeoff between the performance of voice and data traffics for given inpur traffics and link capacity. In addition, it has been found that the average queueing delay of data traffic is longer than the maximum buffer size, when the gain of time assignment speech interpolation(TASI) is more than two and the number of voice users is small.

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The Motion Estimator Implementation with Efficient Structure for Full Search Algorithm of Variable Block Size (다양한 블록 크기의 전역 탐색 알고리즘을 위한 효율적인 구조를 갖는 움직임 추정기 설계)

  • Hwang, Jong-Hee;Choe, Yoon-Sik
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.11
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    • pp.66-76
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    • 2009
  • The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

Digital Logic Extraction from QCA Designs (QCA 설계에서 디지털 논리 자동 추출)

  • Oh, Youn-Bo;Kim, Kyo-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.46 no.1
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    • pp.107-116
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    • 2009
  • Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nanoelectronic devices which will inherit the throne of CMOS which is the domineering implementation technology for large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors is proposed. After the gate and interconnect structures of. the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit adder, a bit-serial adder, and an ALU bit-slice. For each design, the digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.